0.13μmdram產(chǎn)品中hsg電容工藝優(yōu)化方案

1、上海交通大學(xué)碩士學(xué)位論文0.13μm DRAM產(chǎn)品中HSG電容工藝優(yōu)化方案姓名：季峰強(qiáng)申請(qǐng)學(xué)位級(jí)別：碩士專(zhuān)業(yè)：軟件工程指導(dǎo)教師：黃其煜;范建國(guó)20080601HSG PROCESS OF 0.13µM DRAM AND THE IMPROVEMENT ABSTRACT New process method and capacitor structure have been used in advanced DRAM manu

2、facture. This paper mainly solves the HSG（Hemispherical-Grain） process issue of 0.13µm stacked-DRAM. The trends of electrode resistance and the issue of DRT failure have highly impacted the capacitance of HSG proces

3、s tool and the yield of production wafer. So the HSG process method has been studied and 2 relations are found in HSG process .One is the relation between HSG thickness and capacitance, the other is the relation between

4、HSG thickness and DRT ((Data retention fail) failure. Base on these data analysis, the deposition time tuning of base POLY is used to solve the trends of electrode resistance. The decrease of HSG thickness and the enlarg

5、ement of capacitance structure CD are used to solved the DRT failure. After these actions are taken, HSG batch size has been improve from 1 lot to 3 lots and DRT failure is nearly 0%. So the HSG tool capacitance has been