鎖相環(huán)設(shè)計(jì)外文翻譯

1、<p><b>　　外 文 翻 譯</b></p><p>　　原文1： Frequency Modulation in Microwave Phase </p><p>　　Lock Loop Synthesizers </p><p>　　譯文1： 微波鎖相回路合成器的調(diào)頻

2、 </p><p>　　原文2： The Design of A Low-Power Low-Noise Phase </p><p>　　Lock Loop </p><p>　　譯文2： 低功率低噪聲的鎖相環(huán)的設(shè)計(jì) </p>&l

3、t;p>　　Frequency Modulation in Microwave Phase Lock Loop Synthesizers</p><p>　　Abstract — This paper shows, that frequency modulation bandwidth of phase locked controlled oscillator (CO) can be simple expa

4、nded using precorrecting circuit (corrector) connected to control port of oscillator. A method is presented of calculation of corrector according to exact PLL and frequency response of modulation channel, with experiment

5、al demonstration presented of adequacy of described technique being shown. </p><p>　　Index Terms — Microwave PLL synthesizer, frequency modulation, maximum deviation, modulation bandwidth. </p><p&

6、gt;　　I. INTRODUCTION</p><p>　　In many microwave systems the synthesizer must generate frequency modulated signal in addition to monochromatic signal generation, its main function. Solution of this problem in

7、 case of phase lock loop (PLL) synthesizer becomes complicated due resistance of PLL to the CO modulation, as an automatic control system. The most difficulty is the expansion of modulation band and the modulation index

8、range. The purpose of this paper is contribution in solution of these problems. </p><p>　　II. TARGET SETTING</p><p>　　It is well known that frequency modulation possibility of phase locked CO is

9、 limited by cutoff band. Modulation bandwidth corner is equal to PLL angular frequency [1]. In band above cutoff the loop makes no resistance to the CO modulation, but below cutoff its resistance increases when modulatin

10、g frequency decreases. Thus, modulation bandwidth of CO must be widened up to down the PLL angular frequency. It can be made by three issues:</p><p>　　? By decrease of PLL cutoff frequency; </p><p

11、>　　?by impact modulating signal into PLL: modulation of the reference frequency, manipulation of feedback division ratio, addition of the modulating signal to control signal of phase detector; </p><p>　　?

12、by application of linear precorrection to modulating signal for compensation of high-pass properties of PLL [2,3]. </p><p>　　Further the last method is considered. It is more effective as it makes no worse o

13、n dynamic and spectral purity characteristics of PLL synthesizer like first method and has no limitation of modulation bandwidth above like second way. </p><p>　　III. MATHEMATICAL DESCRIPTION OF CORRECTOR MO

14、DEL</p><p>　　To improve the modulation sensitivity of CO an active corrector instead the passive corrector [2] is proposed in Fig. 1. </p><p>　　Fig. 1. Corrector schematic</p><p>　　

15、Modulating signal comes to input 1. PLL control signal comes to input 2. Driving signal for CO goes out through output 3. </p><p>　　A. Small signal model </p><p>　　Corrector transfer function K1

16、(p) from input 1 to output 3 is represented by: </p><p>　　where a, c are gain factors of third stage at low and high frequencies respectively; τ is high frequency time constant of third stage; k is depth of

17、dip of response curve in PLL corner frequency area; b is gain factor of first stage at high frequencies; τ1, τ2 are low and high frequency time constants of dip of response curve respectively. Parameters in (1) can be se

18、lected in case of an exact PLL and modulation channel requirements. </p><p>　　B. Large signal model </p><p>　　Maximum deviation ΔFmax is limited by several factors, which are bound with nonlinea

19、r distortions of modulated signal envelope. These distortions appear in such cases as: </p><p>　　-voltage or current operational amplifier (opamp) saturation; </p><p>　　-CO frequency obtain the

20、corner of regulation curve; </p><p>　　-appearance of dynamic distortion of opamp. </p><p>　　In first case the maximum deviation with voltage saturation is: </p><p>　　where Usat is t

21、he saturation voltage of opamp; Kv is CO tuning sensitivity; KL(p) is closed PLL transfer function. </p><p>　　In second case maximum deviation is constant equal to distance between average CO frequency and n

22、earest corner of CO regulation curve. In third case maximum deviation is represented by [4] </p><p>　　where S is slew rate of opamp. </p><p>　　IV. CORRECTOR DESIGN AND TEST</p><p>　

23、　Fig. 2 shows the calculated and experimental frequency responses of modulation channel with and without corrector. PLL cutoff frequency is 100 kHz, phase margin – 45°, CO tuning sensitivity – 95 MHz/V. CO lag is no

24、t allowed. </p><p>　　Fig. 2. Frequency responses of modulation channel normalized to CO tuning sensitivity </p><p>　　Fig. 3 shows calculated and experimental frequency responses of maximum devia

25、tion for all types of distortions: solid curve – for first, dotted curve – for second and chain line – for third. Calculation was made for opamp AD829 with Usat=12V. Distance between average CO frequency and nearest corn

26、er of CO regulation curve is 50 MHz. </p><p>　　From Fig. 2 and 3 is seen that modulation cannel bandwidth with corrector at maximum deviation 100 kHz is of 1,5 kHz facing 100 kHz without corrector. Dynamic d

27、istortions in opamp don’t appear in comparison with two other types. In the fig. 2 experimental curve is close to calculated one. In Fig. 3 experimental curve differs from calculated one because current saturation of opa

28、mp has been appeared. </p><p>　　V. CONCLUSIONS</p><p>　　Applying an introduced corrector in PLL synthesizer one can expand the modulation bandwidth considerably. Here the simple schematic soluti

29、on and low-cost elements can be used. A calculation method is simple and unlike described one in [3] incorporates the calculation of maximum frequency deviation. </p><p>　　Fig. 3. Maximum deviation frequency

30、 responses</p><p>　　作者：Andrew V. Gorevoy</p><p><b>　　國籍：Russia</b></p><p>　　出處：Siberian Conference on Control and Communications SIBCON–2009</p><p>　　微波鎖相環(huán)合

31、成器的頻率調(diào)制</p><p>　　摘要：本論文表明，通過使用連接預(yù)先校正的電路來控制振蕩器的端口，柏鎖可控制振蕩器的調(diào)頻寬帶就能夠很容易被擴(kuò)展。根據(jù)精確的鎖相回路和錄放幅頻響應(yīng)的調(diào)制通道，校正者提出了一種計(jì)算方法，同時(shí)提出充足的所示被描述技術(shù)的實(shí)驗(yàn)性說明。</p><p>　　索引詞：微波鎖相回路合成器，調(diào)頻，最大偏差，調(diào)制帶寬</p><p><b>

32、　　I.介紹</b></p><p>　　在許多微波系統(tǒng)中，合成器必須產(chǎn)生調(diào)頻信號，不僅僅是產(chǎn)生單頻信號這一主要功能。由于阻止鎖相回路轉(zhuǎn)到調(diào)制可控振蕩器是一個(gè)自動控制系統(tǒng)，因此解決此情況下的鎖相環(huán)合成器這一問題就變得復(fù)雜了。而最大的困難是調(diào)制帶寬和調(diào)制索引范圍的擴(kuò)展。因此，本文的目的在于解決這些問題。</p><p><b>　　II.設(shè)定目標(biāo)</b>&l

33、t;/p><p>　　相位可控振蕩器的調(diào)頻可能性是由截止波段所限制，這是人所共知的。調(diào)制帶寬角等于鎖相環(huán)角頻率。在截止以上的波段，這個(gè)回路對可控振蕩器的調(diào)制不作任何抵抗。但低于它的波段，調(diào)制頻率降低時(shí)，阻力就會增加。因此，振蕩器的調(diào)制帶寬必須擴(kuò)大到能夠降低鎖相環(huán)的角頻率。它可以通過三個(gè)方法解決：</p><p>　　·通過降低鎖相環(huán)截止頻率；</p><p>

34、　　·沖撞調(diào)制信號進(jìn)入鎖相回路：調(diào)節(jié)相關(guān)頻率，控制回應(yīng)分割比率，除了調(diào)制信號來控制相位檢測器；</p><p>　　·應(yīng)用信號調(diào)制的線性預(yù)先校正來補(bǔ)償高通的鎖相環(huán)屬性。</p><p>　　進(jìn)一步考慮最后一種方法。它更有效是因?yàn)樗竦谝环N方法一樣，沒有使鎖相環(huán)合成器的動力特性和光譜純度特性變得更糟糕，而且如第二種方法一樣，對調(diào)制寬帶沒有限制。</p>&l

35、t;p>　　III.校正模型的精確描述</p><p>　　為了改進(jìn)振蕩器的調(diào)制靈敏度，使它從被動相關(guān)器成為主動相關(guān)器，如圖1所示：</p><p><b>　　圖1 校正示意圖</b></p><p>　　調(diào)制信號進(jìn)入輸入端1，鎖相環(huán)控制信號進(jìn)入輸入端2，振蕩器的驅(qū)動信號通過輸出端3出去。</p><p><

36、;b>　　小信號模型</b></p><p>　　從輸入端1到輸出端3的校正傳遞函數(shù)K1（P）的代表方式是：</p><p>　　其中 是各自低頻和高頻中第三級的增益因子， 是第三階段的高頻時(shí)間常數(shù)， 是在鎖相環(huán)角頻率區(qū)域的響應(yīng)曲線浸深度， 為在高頻率第一階段的增益因素， 分別是低頻和高頻浸響應(yīng)曲線的時(shí)間常數(shù)。如果需要精確的鎖相環(huán)和調(diào)制通道，就可以選擇參數(shù)（1）。<

37、/p><p><b>　　大信號模型</b></p><p>　　最大偏差 被一些因素所限制，這些因素與調(diào)制信號包絡(luò)的非線性失真密切相關(guān)。這些失真出現(xiàn)在這些情況下：</p><p>　　-電壓或電流運(yùn)算放大器的飽和度；</p><p>　　-振蕩器頻率得到電壓調(diào)整曲線角；</p><p>　　-出現(xiàn)電

38、壓或電流運(yùn)算放大器的動態(tài)失真。</p><p>　　在第一種情況下，電壓飽和度的最大偏差為：</p><p>　　其中 是運(yùn)算放大器的飽和電壓， 為振蕩器調(diào)整靈敏度， 是閉合鎖相環(huán)的傳遞函數(shù)。</p><p>　　在第二種情況下，最大偏差等于平均振蕩器頻率和振蕩器電壓調(diào)制曲線最近角之間的距離的常數(shù)。第三種情況的最大偏差表達(dá)方式為</p><p&g

39、t;　　其中S是運(yùn)算放大器的轉(zhuǎn)換速率。</p><p>　　IV.校正的設(shè)計(jì)與測驗(yàn)</p><p>　　圖2顯示了有無校正的調(diào)制通道的計(jì)算和實(shí)驗(yàn)頻率響應(yīng)。鎖相環(huán)的截止頻率為100kHz，相位差度為-45度，振蕩器調(diào)整靈敏度為-95MHz/V，振蕩器滯后是不允許的。</p><p>　　圖2 調(diào)制通道的頻率響應(yīng)歸到振蕩器調(diào)整敏感度</p><p&g

40、t;　　圖3顯示計(jì)算與實(shí)驗(yàn)頻率響應(yīng)的最大偏差的所有失真類型：實(shí)線為第一，點(diǎn)線為第二，鏈線為第三名。計(jì)算是由運(yùn)算放大器AD829與Usat=12V組成的。平均振蕩器頻率和振蕩器電壓調(diào)制曲線最近角之間的距離是50MHz。</p><p>　　從圖2和圖3看出，在最大偏差100KHz帶有校正器的調(diào)頻寬帶是1，相對100KHz，5KHz是沒有校正器的。與其他兩個(gè)類型相比較，運(yùn)算放大器中的動態(tài)失真是不出現(xiàn)的。在圖2中，實(shí)驗(yàn)

41、曲線接近計(jì)算值。在圖3中，實(shí)驗(yàn)曲線與計(jì)算值不同是因?yàn)檫\(yùn)算放大器的電流飽和了。</p><p><b>　　V.結(jié)論</b></p><p>　　在鎖相環(huán)合成器中引用一個(gè)校正器，調(diào)制寬帶可以相當(dāng)大地被擴(kuò)展。在這里，簡單的圖表解決方案和低成本的元素都可以使用。一個(gè)計(jì)算方法很簡單，不像[3]中所描述的一個(gè)整合了最大頻率偏差的計(jì)算。</p><p>　

42、　圖3 最大偏差頻率響應(yīng)</p><p>　　作者：安德魯.格里維</p><p><b>　　國籍：俄羅斯</b></p><p>　　出處：SIBCON-2009西伯利亞控制與通信會議</p><p>　　The Design of A Low-Power Low-Noise Phase Lock Loop</

43、p><p>　　Abstract :A phase lock loop is a closed-loop system that causes one system to track with another. More precisely, a PLL can be perceived as a circuit synchronizing an output signal with a reference or i

44、nput signal in frequency as well as phase. High-performance phase lock loops are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and synchronize between f

45、unction units and ICs As the digital system grows the role of phase lock loop </p><p>　　Keywords:Phase Lock loop (PLL), Phase Frequency Detector (PFD), Voltage to Current converter (V2I), Current Controlled

46、Oscillator (ICO) </p><p>　　1. Introduction </p><p>　　A PLL is essentially a negative feedback loop that locks the on-chip clock phase to that of an input clock or signal [1]. High-performance PL

47、L’s are widely used within a digital system for clock generation, timing recovery, and to efficiently sequence operations and synchronize between function units and ICs [2]. Clock frequencies and data rates have been inc

48、reasing with each generation of processing technology and processor architecture. Within these digital systems, well-timed clocks are gener</p><p>　　2. PLL Definition </p><p>　　A PLL can be perc

49、eived as a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as phase [4]. In the synchronized state, often referred to as “the locked state”, the p

50、hase error between the output signal and the input or reference signal remains constant or is zero However, if in the process due to some discrepancy a phase error builds up, a control mechanism gets triggered, which act

51、s on the oscillator to counter-balance the </p><p>　　such a manner that it is reduced to minimum until it is matched. As, the control system actually locks (matches) the phase of the output signal to the pha

52、se of the reference or the input signal. Hence the name, “Phase-locked loop”. It is important here to note that, the PLL not only sets a fixed relationship between its output clock phase and the input or reference clock

53、phase but also tracks the subsequent phase changes that are within its bandwidth. Due to its characteristics, the PLL is used </p><p>　　3. PLL Components </p><p>　　A basic block of PLL as shown

54、in figure 1 consists of five fundamental blocks, namely, Phase detector, Charge pump, Loop filter, voltage controlled oscillator and the divider network. The individual building blocks are explained to understand the gen

55、eric block diagram representation of a basic PLL in a much wider sense [7]. </p><p>　　Figure 1 : Basic Compoments of PLL</p><p>　　3.1 Phase Detector </p><p>　　The primary purpose of

56、 the phase detector (PD) is to compare the phase of the periodic input signal against the phase of the voltage controlled oscillator (VCO) and accordingly generates a subsequent error signal which is proportional to the

57、phase deviation between them. The difference voltage (error signal) is then filtered by the loop filter and applied to the divided down output from VCO [8]. </p><p>　　3.2 Charge Pump </p><p>　　T

58、he charge pump coupled to a phase detector block is a vital building block in the design topology. It helps provide an effective controlling mechanism for the charging and discharging of the low pass filter. It is used t

59、o manipulate the amount of charge on the loop filter’s capacitors depending on the lead (UP) and lag (Down) error signals generated from the phase detector [8]. </p><p>　　3.3 Loop filter </p><p>

60、;　　The Loop filter included in design architecture is a passive device comprising of two capacitors and a resistor. The output voltage generated from the loop filter informs the VCO to adjust its frequency (increase/decr

61、ease) in such a manner that the voltage output is maintained proportional to the charge of the capacitors. The introduction of additional capacitor serves to reduce the incoming noise from the previous components and fur

62、ther helps in the reduction of the lock time. </p><p>　　It is imperative to note that the output translated from the phase detector consists of a DC component and a superimposed AC component. Thus, the low p

63、ass filter is one of the key design components which serve to effectively filter out the undesired AC component and provides a steady control voltage for the VCO to operate with. </p><p>　　3.4 Voltage Contro

64、lled Oscillator </p><p>　　The voltage controlled oscillators is the most important device component of this prolific feedback system that helps produce the essential frequency output (Fout) of the PLL. Depen

65、ding on the control voltage of the low pass filter, the VCO generates the frequency that matches the reference signal. </p><p>　　3.5 Loop Divider </p><p>　　An efficient Divider circuit provides

66、a greater degree of flexibility to the design engineers by allowing them to effectively operate a given PLL at a higher frequency. Being an integral part of the feedback loop, the divider configuration also serves as an

67、optimum solution to reduce the frequency from the VCO into a value that can be comparable to the reference signal. Thus, as the operation range for the crystals is usually not more than a few 100 MHz, while the VCO’s gen

68、erally works in the ra</p><p>　　4. Proposed PLL Architecture and sub blocks </p><p>　　Figure 2: Proposed PLL Architecture</p><p>　　The proposed PLL architecture is shown in figure 2

69、. </p><p>　　4.1 Implementation/Redesign of High Speed Low </p><p>　　Power Phase Frequency Detector Implementation of low power high speed PFD using TSPC (True Single Phase Clock) positive edge t

70、riggered D Flip Flop is shown in figure 3. The operating range of this PFD is up to 1 GHz with no extra circuits added. The PFD are designed using 0.18u technology with 1.8V as the power supply. </p><p>　　Fi

71、gure 3: Implementation of TSPC D flip flop with low true Reset</p><p>　　From the architecture of FPD the data pin of D flip flop is always connected to VDD. The node voltage node X is always 0, also the char

72、ges only when my D goes to 0 (not possible in this case since D is connected to Vdd). The transistors before node X and also below Node X can be removed. The proposed architecture is shown in figure 4. The Proposed archi

73、tecture reduces dead zone (less than 30ps), steady state error, area and power consumed. </p><p>　　Figure 4: Proposed architecture of TSPC D flip flop with low true Reset</p><p><b>　　4.2 V

74、2I </b></p><p>　　The Voltage to current converter block is used to convert voltage (control voltage Vctrl) to current. IICO the current generated from the V2I block is used to control the output freque

75、ncy of the Current Controlled Oscillator. </p><p>　　Fout is the output frequency of the ring oscillator. N is the number of stages in the ring oscillator. Ctotal is the total node capacitance between two cur

76、rent starved inverters. As the current IICO increases the output frequency increases. Now the question is how to increase the current linearly such that the Fout increases linearly. The device to which the Vctrl is appli

77、ed should have a linear relationship between the current produced and the voltage applied to the device. MOS is a non – linea</p><p>　　Figure 5: Proposed Architecture for V2I.</p><p>　　The propo

78、sed architecture for V2I block is shown in figure 5. The value of IICO is determined by the control voltage Vctrl generated from loop filter. Vctrl is applied to node A. The current sources B and C sinks and current sour

79、ce A sources equal amount of current. IICO is proportional to the current flowing through the resistor. The linear increase of IICO with applied Vctrl is shown in figure 6. </p><p>　　Figure 6: Linear increas

80、e of current in ICO</p><p>　　4.3 Feedback </p><p>　　The Feedback block helps in linearizing gain and to remove the non linearity of the VCO. The gain of the charge pump is controlled by current

81、controlled oscillator input current in a manner that linearizes the combination of charge pump and current controlled oscillator [10]. The proposed architecture for feedback block is shown in figure 7. </p><p&

82、gt;　　Figure 7: Proposed Architecture for V2I.</p><p>　　The values of the current sources are set so that when the gain of VCO starts reducing the gain of charge pump should start increasing, i.e. the total l

83、oop gain remains constant. The point A in figure 8 represents the point where oscillator gain decreases and the charge pump current increases. </p><p>　　Figure 8: Linear increase of charge pump current.</

84、p><p>　　4.4 Current Controlled Oscillator </p><p>　　The Current starved Oscillator operates similar to that of the ring oscillator. It has additional control of the output frequency. The design con

85、sists of current starved inverters and Schmitt trigger inside the loop. The proposed architecture for ICO is shown in figure 9. The output of the current starved VCO is buffered through inverter to connect it to large lo

86、ad. </p><p>　　Figure 9: Linear increase of charge pump current.</p><p>　　The Schmitt trigger is designed with upper and lower voltage levels set to 1.2V and 600mv. The Schmitt trigger acts like

87、inverter with hysteresis .It helps in reducing Phase Noise. </p><p>　　Figure 10: Linear increase of charge pump current.</p><p>　　The phase noise for the ICO without Schmitt trigger is shown in

88、figure 10. </p><p>　　Figure 11: Linear increase of charge pump current.</p><p>　　Phase noise for the ICO Schmitt trigger is shown in figure 9. It’s clear from the figures that Schmitt trigger he

89、lps in reducing the phase noise and also removes the amplitude distortion form the output of the oscillator. </p><p>　　Figure 12 shows the output of PLL in locked state.</p><p>　　Figure 12: Line

90、ar increase of charge pump current.</p><p>　　作者：Abishek Mann, Amit Karalkar, Lili He, and Morris Jones</p><p><b>　　國籍：USA</b></p><p>　　出處：Department of Electrical Engine

91、ering San Jose State University, CA, USA</p><p>　　低功率低噪聲鎖相環(huán)的設(shè)計(jì)</p><p>　　摘要：鎖相環(huán)是引起一個(gè)系統(tǒng)跟蹤另一個(gè)系統(tǒng)的閉環(huán)系統(tǒng)。更確切地說，一個(gè)鎖相環(huán)可看作是一個(gè)在頻率和相位中同步輸出相關(guān)信號或輸入信號的電路。高性能鎖相回路在時(shí)鐘脈沖振蕩和定時(shí)恢復(fù)的數(shù)字系統(tǒng)中被廣泛使用，并有效地按順序運(yùn)營，在功能單位和內(nèi)部通信系統(tǒng)之間

92、同步進(jìn)行。鎖相環(huán)的作用隨著數(shù)字系統(tǒng)的增長而增加。在鎖相回路中，實(shí)現(xiàn)低跳動和低相位噪聲并且更小的面積和功耗消費(fèi)是個(gè)挑戰(zhàn)。目前的研究涉及到個(gè)別區(qū)塊鎖相環(huán)的界定方法和重新設(shè)計(jì)，以改善其特性。更多個(gè)別區(qū)塊的特殊重設(shè)計(jì)，如：以減少面積和靜態(tài)相位誤差的相位頻率檢測器，電壓電流變頻器來線性增加電流輸入到電流控制振蕩器，電流控制振蕩器來降低相位噪聲，振幅失真，面積和功耗。我們還引入額外反饋回路，以一個(gè)增加該充電泵的獲得的方式，該方式使整體回路增益比寬帶

93、更寬。這個(gè)結(jié)果在如低跳動，低相位噪聲，低區(qū)域和功耗等鎖相環(huán)特點(diǎn)中顯示重大的改善。</p><p>　　關(guān)鍵詞：鎖相回路，相位頻率檢測器器，電壓至電流變頻器，電流控制振蕩器</p><p><b>　　1．簡介</b></p><p>　　鎖相環(huán)本質(zhì)上是一個(gè)負(fù)反饋回路，鎖住時(shí)鐘相位芯片到一個(gè)輸入時(shí)鐘或信號。高性能鎖相回路在時(shí)鐘脈沖振蕩和定時(shí)恢復(fù)的

94、數(shù)字系統(tǒng)中被廣泛使用，并有效地按順序運(yùn)營，在功能單位和內(nèi)部通信系統(tǒng)之間同步進(jìn)行。時(shí)鐘頻率和數(shù)據(jù)速率跟著每代加工技術(shù)和處理器架構(gòu)一直在增加。在這些數(shù)字系統(tǒng)中，準(zhǔn)時(shí)的時(shí)鐘由鎖相回路產(chǎn)生，然后分布在時(shí)鐘緩沖器芯片中。該系統(tǒng)時(shí)鐘頻率的快速增加使得在產(chǎn)生和分布低相位噪聲和低功率的時(shí)鐘時(shí)具有挑戰(zhàn)。</p><p><b>　　2．鎖相環(huán)的定義</b></p><p>　　一個(gè)鎖相

95、環(huán)可被看作是一個(gè)在頻率和相位中同步輸出相關(guān)信號（由振蕩器產(chǎn)生）或輸入信號的電路。在同步狀態(tài)里，通常被稱為“鎖定狀態(tài)“時(shí)，輸出信號與輸入或參考信號之間的相位誤差保持不變或者為零。但如果在這一過程由于一些差異，相位誤差累積，一種控制機(jī)制被觸發(fā)，這使振蕩器在所造成的相位誤差抵消制衡起到功效，這是減少到最低限度直到它被匹配的一種方式。正如，控制系統(tǒng)實(shí)際上鎖?。ㄆヅ洌┹敵鲂盘柕南辔粸閰⒖蓟蜉斎胄盘栂辔?。因此得名“鎖相環(huán)“。這里需要重點(diǎn)注意，鎖相環(huán)

96、不僅設(shè)置一個(gè)輸出時(shí)鐘相位和輸入或者參考時(shí)鐘相位之間的固定關(guān)系，而且也跟蹤下一階段其帶寬的相位變化。由于其特性，鎖相環(huán)被用于通信網(wǎng)絡(luò)系統(tǒng)和其他需要一個(gè)時(shí)鐘恢復(fù)，倍頻器和數(shù)據(jù)同步的電路。它為系統(tǒng)和電路工程師們提供了具有生成高性能定時(shí)時(shí)鐘芯片數(shù)字系統(tǒng)更大程度上的自由。</p><p>　　3．鎖相環(huán)的組成部分</p><p>　　一個(gè)鎖相環(huán)的基本塊，如圖1所示，包括五個(gè)基本塊，即，鑒相器，充電泵

97、，環(huán)路濾波器，電壓控振蕩器和分頻器網(wǎng)絡(luò)。個(gè)別建筑塊用來解釋理解一個(gè)在更廣泛意義上的基本鎖相環(huán)通用的框圖。</p><p>　　圖1 鎖相環(huán)的基本組成部分</p><p><b>　　3.1鑒相器</b></p><p>　　鑒相器的主要目的是比較定期輸入信號的相位和電壓控制振蕩器的相位，隨后相應(yīng)地產(chǎn)生一個(gè)它們之間相位偏離成比例的錯(cuò)誤信號。該差分

98、電壓（誤差信號）然后在回路濾波器里過濾，并應(yīng)用于從電壓控制振蕩器中分下來的輸出。</p><p><b>　　3.2充電泵</b></p><p>　　連結(jié)到一個(gè)鑒相器區(qū)塊的充電泵是設(shè)計(jì)拓?fù)浣Y(jié)構(gòu)中的重要組成部分。它有助于提供一個(gè)有效的控制機(jī)制，在低濾過器中充電和不充電。它是用來控制環(huán)路濾波器的電容充電量，該容量取決于由鑒相器產(chǎn)生的領(lǐng)先（上）和滯后（下）的錯(cuò)誤信號。&l

99、t;/p><p><b>　　3.3環(huán)路濾波器</b></p><p>　　包括在設(shè)計(jì)架構(gòu)中的環(huán)路濾波器是一個(gè)由兩個(gè)電容器和一個(gè)電阻器組成的被動設(shè)備。在環(huán)路濾波器中生成的輸出電壓通知電壓控制振蕩器來調(diào)整頻率（增加/減少），在這樣一種方式中，輸出電壓與電容器充電量成正比例保持。引進(jìn)額外電容的作用是降低以前元件的噪聲傳入，并進(jìn)一步幫助減少鎖定時(shí)間。必須需要注意的是從鑒相器中轉(zhuǎn)

100、換成的輸出由一個(gè)直流分量和一個(gè)疊加交流分量組成。因此，低通濾波器是一個(gè)關(guān)鍵的設(shè)計(jì)組件，能夠有效地過濾出不受歡迎的交流分量，提供了一個(gè)使電壓控制振蕩器正常運(yùn)作的穩(wěn)定控制電壓。</p><p>　　3.4電壓控制振蕩器</p><p>　　電壓控制振蕩器是這個(gè)多產(chǎn)的反饋系統(tǒng)中最重要的設(shè)備組件，它能幫助產(chǎn)生必要的鎖相環(huán)輸出頻率。依據(jù)低通濾波器中的控制電壓，電壓控制振蕩器產(chǎn)生了與參考信號相匹配的頻

101、率。</p><p><b>　　3.5環(huán)分頻器</b></p><p>　　一個(gè)高效的分頻器電路給設(shè)計(jì)工程師提供了更大程度的靈活性，讓他們在給定的更高頻率的鎖相環(huán)中有效地工作。作為一個(gè)反饋環(huán)路的必需組成部分，分頻置配置也可作為減少頻率從電壓控制振蕩器到與參考信號可比較的一個(gè)值的最佳的解決方案。因此，晶體的操作范圍通常不超過100MHz，而電壓控制振蕩器的一般運(yùn)作范圍

102、是10GHz。這個(gè)環(huán)分頻器完成了一個(gè)基本的鎖相環(huán)動態(tài)設(shè)計(jì)。</p><p>　　4．?dāng)M議的鎖相環(huán)架構(gòu)和輔助區(qū)塊</p><p>　　圖2 擬議的鎖相環(huán)架構(gòu)</p><p>　　推薦的鎖相環(huán)架構(gòu)如圖2所示。</p><p>　　4.1高速低功率相位頻率檢波器的實(shí)施/重新設(shè)計(jì)</p><p>　　圖3顯示了使用由D觸發(fā)器引

103、發(fā)的真實(shí)單相時(shí)鐘上升沿來達(dá)到高速低功率相位頻率檢波器的實(shí)現(xiàn)。如圖3所示。無需額外電路的補(bǔ)充，該相位頻率檢波器的工作范圍可高達(dá)1GHz。設(shè)計(jì)這個(gè)檢波器使用了0.18u的技術(shù)和1.8V的能量供給。</p><p>　　圖3 低失真復(fù)置D觸發(fā)器真實(shí)單相時(shí)鐘的實(shí)現(xiàn)</p><p>　　從平面顯示器的結(jié)構(gòu)看，D觸發(fā)器的數(shù)據(jù)插頭始終連接到電壓源。節(jié)點(diǎn)電壓節(jié)點(diǎn)X始終為0，而且只有D變?yōu)?時(shí)才充電（在此情