外文翻譯-- 數(shù)字頻率合成器

1、<p>　　附 錄2：外文原文，譯文</p><p>　　Modulating Direct Digital Synthesizer</p><p>　　In the pursuit of more complex phase continuous modulation techniques, the control of the output waveform becomes

2、 increasingly more difficult with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goal

3、s is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quant</p><p>　　This article is intended to gi

4、ve the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable gate array fro

5、m QuickLogic.</p><p>　　A basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinu

6、soidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias components. Fig

7、ure 1 is a basic block diagram of a typical DDS system design.The generation of the output carri</p><p>　　FIGURE 1: Typical DDS System. </p><p>　　FIGURE 2: Typical NCO Design. </p><p&

8、gt;　　To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of the NCO design

9、 are best understood when compared to the graphical representation of Euler’s formula ej wt = cos( wt) + jsin( wt). The graphical representation of Euler’s formula, as shown in Figure 3, is a unit vector rotating around

10、the center axis of the real and imaginary plane at a velocity of </p><p>　　This frequency word is continuously accumulated with the last sampled phase value by an N bit adder. The output of the adder is samp

11、led at the reference sample clock by an N bit register. When the accumulator reaches the N bit maximum value, the accumulator rolls over and continues. Plotting the sampled accumulator values versus time produces a saw t

12、ooth wave form as shown below in Figure 3. </p><p>　　FIGURE 3 Euler’s Equation Represented Graphically</p><p>　　The sampled output of the phase accumulator is then used to address a ROM lookup t

13、able of sinusoidal magnitude values. This conversion of the sampled phase to a sinusoidal magnitude is analogous to the projection of the real or imaginary component in time. Since the number of bits used by the phase ac

14、cumulator determines the granularity of the frequency adjustment steps, a typical phase accumulator size is 24 to 32 bits. Since the size of the sinusoidal ROM table is directly proportional to the </p><p>　

15、　Since an NCO outputs a carrier based on a digital representation of the phase and magnitude of the sinusoidal wave form, designers have complete control over frequency, phase, and even amplitude of the output carrier. B

16、y adding a phase port and a phase adder to the basic NCO design, the output carrier of the NCO can be M array phase modulated where M equals the number of phase port bits and where M is less than or equal to the Y number

17、 of bits used to address the sinusoidal ROM table. For system</p><p>　　Although DDS systems give the designer complete control of complex modulation synthesis, the representation of sinusoidal phase and magn

18、itude in a non-linear digital format introduces new design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error. </p><p>　　To understand the effe

19、cts of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at

20、a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO

21、input reference sampling clock. Figure</p><p>　　Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of this sinusoid is

22、an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the sampling clock

23、edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequen</p><p>　　The frequency domain results are the impulse function at the fundamental fre

24、quency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at: </p><p>　　K*Fclk - F

25、out </p><p>　　K*Fclk + Fout </p><p>　　Where K = ... -1, 0 , 1, 2 ..... and K = 0 is the NCO sinusoid fundamental frequency </p><p>　　Fout is the specified NCO sinusoid output freque

26、ncy </p><p>　　Fclk is the NCO reference clock frequency </p><p>　　FIGURE 4 NCO Output Representation Time and Frequency Domain</p><p>　　The DAC of the DDS system takes the NCO outpu

27、t values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and hold circuit that

28、 takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The time domain plot of the DAC processing is the convolution of the NCO sampled outpu

29、t values with a</p><p>　　Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)] Where F is the output frequency Fclk is the sample clock frequency </p><p>　　FIGURE 5: DAC Output Representation in Time and Fre

30、quency Domain </p><p>　　Aside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious response of a D

31、DS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC. </p><

32、;p>　　As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator introduces a pha

33、se truncation. When a frequency word containing a non-zero value in the lower (N-Y-1:0) bits is loaded into the DDS system, the lower non-zero bits will accumulate to the upper Y bits and cause a phase truncation. The fr

34、equency at which the phase truncation occurs can be calculated by th</p><p>　　Ftrunc = FW(N-Y- 1:0)/2N-Y* Fclk. </p><p>　　A phase truncation will periodically (at the Ftrunc rate) phase modulate

35、 the output carrier forward 2p/28 to compensate for frequency word granularity greater than 2Y. The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental.</p><p>

36、;　　These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be - 20log(2Y)dBc. A sample output of a phase truncation spur is shown in Figure 5. &l

37、t;/p><p>　　In a typical NCO design, the ROM sinusoidal table will hold a ¼ sine wave (0 , p/2) of magnitude values. The ROM table is generated by taking all possible phase value addresses and map to a real

38、 magnitude sine value rounded to the nearest D bits. Thus, the maximum error output is ±- ½ LSB giving a worst case spur of -20log(2D)dBc. </p><p>　　Like the NCO ROM table, a DAC quantizes the digi

39、tal magnitude values. A DAC, however, outputs an analog voltage corresponding to the digital input value. When designing the NCO sinusoidal ROM table, one should take some empirical data on the DAC linearity to better un

40、derstand the interaction between the ROM table and the DAC. The quantization for a DAC is specified against an ideal linear plot of digital input versus analog output. Two linearity parameters, differential and integral

41、linearity, a</p><p>　　Differential linearity is the output step size from bit to bit. A DAC must guarantee a differential linearity of a maximum 1 LSB. When an input code is increased, the DAC output must in

42、crease. If the DAC voltage does not increase versus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only accurate to 9 o

43、r less bits. The number of accurate output bits will specify the DDS spurious performance as -2</p><p>　　Integral linearity is a measure of the DAC’s overall linear performance versus an ideal linear straigh

44、t line. The straight line plot can be either a “best straight line” where DC offsets are possible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and max output values

45、. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output</p><p>　　Other DAC character

46、istic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board components external

47、to the DAC such as an RF transformer, board layout issues, attenuation pads etc. </p><p>　　Given the complexities of the DDS system, engineers should consider implementing the design using separate devices f

48、or the numerically controlled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is compact enough to be practical as an en

49、d-solution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a single-chip mixed signal ASIC. </p><p>　　The author developed a version of the design using a Harris HI5721 eva

50、luation board for the DAC. The NCO at the heart of the DDS design, and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). This FPGA, a QL16x

51、24B 4000-gate device, was chosen for its high performance, ease-of-use, and powerful development tools. </p><p>　　The NCO design included following:</p><p>　　Developed in Verilog with the 8 bit

52、CLA adder schematic </p><p>　　captured and net listed to Verilog</p><p>　　32 bit frequency word input </p><p>　　32 phase accumulator pipelined over 8 bits</p><p>　　8 bi

53、t phase moudulation word input</p><p>　　8 bit sine ROM look-up table</p><p>　　The design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickLogic’s macro li

54、brary netlisted to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with the design run

55、ning at an impressive 45MHz as predicted by the software simulation tools. </p><p>　　Plots used in the article to illustrate DDS performance parameters were provided from the test configuration. </p>

56、<p>　　Figure 6 below shows the external IO interface to the NCO design .The function of each signal is described in the following table.</p><p>　　Signal Function Table </p><p>　　Figure 6: T

57、he External IO Interface </p><p>　　Top Level (dds.v) </p><p>　　The top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block. </p><p&

58、gt;　　PN Generator (pngen.v) </p><p>　　This module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK input to clock t

59、wo Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs. </p><p>　　The lower level block of this NCO design consist of a synchronous frequency word input register, a sy

60、nchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and the PN generator are provided in the followin

61、g sections. </p><p>　　Load Frequency Word (loadfw.v) </p><p>　　The load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input to the 32 bit fw

62、reg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous register fwwrns to pr

63、oduce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, lo</p><p>　　Phase Word Accumulator (phasea.v) </p>&l

64、t;p>　　The phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out port. The sync

65、hronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with the output tied back to the

66、 A input of the CLA adders. The carry output of the CLA adders is reg</p><p>　　Load Phase Word (loadpw.v) </p><p>　　The load phase word block is a synchronizing loading circuit. The PHASEWORD[7:

67、0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that is used in conju

68、nction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd regist</p><p&

69、gt;　　Phase Modulator (phasemod.v) </p><p>　　The phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase word block. This

70、 module instantiates a CLA adder with the A input tied to the synchronous phase output and the B input tied to the phase accumulator output. The sum output of the adder is registered in the mphsreg register and assigned

71、to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the </p><p>　　Sine Lockup (sinlup.v) </p><p>　　This module takes the modulated ph

72、ase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine ROM table that i

73、n instantiated in this module. The ROM table is reduced to a ¼ of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase input.This module performs the calculations to

74、reconstruct a complete period o</p><p>　　This module manages the address values to the ROM table and the amplitude outputs to form the complete period of the sine wave form. The first process of generating t

75、he sine wave function is the addressing of the ROM table such that phase angles p/2 to p and 3p/2 to 2p are addressed in the reverse order. Reverse addressing is accomplished by simply inverting the ROM table address inp

76、ut vector. The phase modulated address input is inverted when the MODPHASE[6] is one and is then registered in the</p><p>　　Sine ROM Table (romtab.v) </p><p>　　This module is the sine wave form

77、ROM table. This table converts the phase word input to a sine amplitude output. To conserve area, only ¼ of the symmetrical sine wave form is stored in the ROM. The sine values stored in this table are the 0 to p/2

78、 unsigned values quantized to 8 bits. Thus, the ROM table requires a 6 bit phase address input and outputs a 7 bit amplitude output. The sinlup module processes the phase and amplitude values to produce a complete sine p

79、eriod. </p><p>　　Dan Morelli has over 9 years of design and management experience. His areas of expertise include spread spectrum communications (involving GPS, TDRSS, and 802.11), PC chip set and system arc

80、hitecture, cell library development (for ECL devices) and ASIC development. He has been published and has multiple patents awarded and pending. Dan currently works for Accelent Systems Inc., an electronic design consulti

81、ng company, where he is a founder and the VP of Engineering.</p><p>　　數(shù)字頻率合成器 </p><p>　　在探討許多復(fù)雜的相位連續(xù)的調(diào)制技術(shù)中，對(duì)模擬電路中輸出波形的控制已經(jīng)越來(lái)越困難。在這些設(shè)計(jì)中，使用非線性數(shù)字式設(shè)計(jì)除去電路板需要的調(diào)整額外輸出和溫度。一個(gè)適合這個(gè)目標(biāo)的數(shù)字式

82、設(shè)計(jì)就是直接數(shù)字頻率合成器（DDS）。一個(gè)DDS系統(tǒng)僅僅使用一個(gè)恒定參考時(shí)鐘輸入和將該時(shí)鐘分解為指定的量化數(shù)位頻率輸出或者對(duì)參考時(shí)鐘頻率取樣。這種形式是頻率控制使得DDS系統(tǒng)成為需要精確頻率掃描比如雷達(dá)尖叫聲或者快速頻率計(jì)量器的理想系統(tǒng)。根據(jù)數(shù)字輸入控制字以控制輸出頻率，DDS系統(tǒng)可以用來(lái)當(dāng)作一個(gè)允許精確頻率連續(xù)改變相位的鎖相環(huán)（PLL）。根據(jù)后面的說(shuō)明，我們知道DDS系統(tǒng)還可以使用輸入數(shù)字相位控制字來(lái)控制輸出載波的相位。用數(shù)字式控制載

83、波相位，很容易產(chǎn)生一個(gè)高頻譜密度的相位調(diào)制載波。</p><p>　　本文主旨是給讀者一個(gè)基本的DDS設(shè)計(jì)和寄生輸出響應(yīng)的知識(shí)。本文將展示一個(gè)運(yùn)行于45MHz的快速現(xiàn)場(chǎng)可編輯邏輯器件。</p><p>　　一個(gè)基本的DDS系統(tǒng)包括一個(gè)數(shù)字振蕩器（NCO）用來(lái)產(chǎn)生輸出載波，和一個(gè)數(shù)模轉(zhuǎn)換器（DAC）用來(lái)將從NCO過(guò)來(lái)的數(shù)字式正弦曲線字產(chǎn)生一個(gè)抽樣的模擬載波。當(dāng)DAC的輸出是根據(jù)參考時(shí)鐘頻率的

84、抽樣時(shí)，通常用一個(gè)圓滑波形的低通濾波器來(lái)消除混疊成分。根據(jù)輸入的參考時(shí)鐘抽樣經(jīng)過(guò)NCO來(lái)產(chǎn)生輸出載波。NCO的基本構(gòu)成是一個(gè)相位累加器和一個(gè)正弦ROM查找表。通過(guò)增加NCO的載波相位調(diào)制的輸出能力可以提高DDS系統(tǒng)的設(shè)計(jì)。</p><p>　　為了更好的理解NCO設(shè)計(jì)的各種功能，首先考慮僅包括一個(gè)相位累加器和一個(gè)正弦ROM查找表的基本NCO設(shè)計(jì)。與歐拉公式（Euler’s formula）圖解比較就能最好地理解這

85、兩個(gè)表的NCO設(shè)計(jì)的功能。歐拉公式的圖解如圖3所示，是一個(gè)單位向量繞著實(shí)軸和虛平面的中心以W rad/s的速度轉(zhuǎn)圈。</p><p>　　這個(gè)頻率控制字是最后一個(gè)抽樣相位值通過(guò)一個(gè)N位加法器的連續(xù)地累加而成。加法器的輸出是參考抽樣時(shí)鐘通過(guò)一個(gè)N位寄存器的抽樣。當(dāng)累加器達(dá)到N位最大值的時(shí)候，累加器翻轉(zhuǎn)然后繼續(xù)。然后相位累加器的抽樣輸出用來(lái)在一個(gè)正弦量化值表里進(jìn)行查找。抽樣相位到正弦量化的轉(zhuǎn)化可以看作是真實(shí)的或者虛擬

86、的成分及時(shí)地影射。因?yàn)橄辔焕奂悠鞯谋忍匚粩?shù)決定了頻率調(diào)整的步進(jìn)，一個(gè)典型的相位累加器的大小是24到32位。由于正弦ROM表的大小是跟尋址范圍直接成比例的，因此，不是所有相位累加器的24或32位都用來(lái)作為正弦ROM表的地址。僅是相位累加器的高Y（Y〈N〉位是用來(lái)作為正弦ROM表的地址，Y通常不必要等于正弦ROM表的輸出量位D。</p><p>　　因?yàn)橐粋€(gè)NCO輸出的一個(gè)基于一個(gè)數(shù)字表示的相位和正弦波量化形式的載波

87、，所以設(shè)計(jì)者可以完全的控制輸出載波的頻率，相位和幅度。通過(guò)加入一個(gè)相位端口和一個(gè)相位加法器到一個(gè)基本的NCO設(shè)計(jì)中，NCO的輸出載波當(dāng)M等于相位端口數(shù)和M小于或等于Y（用來(lái)作為正弦ROM表的地址位數(shù)）時(shí)可以被M矩陣相位調(diào)制。假如系統(tǒng)設(shè)計(jì)需要幅度調(diào)制如QAM，可以加入一個(gè)量化端口來(lái)調(diào)整正弦ROM表的輸出。注意到這個(gè)端口沒(méi)有在圖2里表示出來(lái)以及這個(gè)特色沒(méi)有在簡(jiǎn)單的快速邏輯FPGA設(shè)計(jì)中論證。最后，頻率是調(diào)制是一個(gè)基本的NCO設(shè)計(jì)給出的。因?yàn)?/p>

88、頻率控制字是跟抽樣時(shí)鐘是同步裝載到DDS的，頻率的轉(zhuǎn)化是相位連續(xù)的。</p><p>　　雖然DDS系統(tǒng)給設(shè)計(jì)者完全地控制復(fù)雜的調(diào)制合成，但是在一個(gè)非線性數(shù)字格式的正弦相位和量級(jí)的表示卻是復(fù)雜的新設(shè)計(jì)。在取樣任何的連續(xù)時(shí)間信號(hào)時(shí)，必須考慮取樣原理和量子化誤差。</p><p>　　為了理解DDS系統(tǒng)中取樣理論的效果，最好看一下時(shí)間和頻率域的DDS合成過(guò)程。就象上面規(guī)定的，通過(guò)以指定的速率累

89、積的形式由NCO產(chǎn)生一個(gè)正弦波然后用一個(gè)相位的值來(lái)定位一個(gè)正弦調(diào)制ROM表的值。因此，NCO本質(zhì)上用一個(gè)正弦波和用NCO的上升或下降沿輸出參考取樣時(shí)鐘對(duì)其取樣。圖4表示在時(shí)間和頻率域里NCO的處理。注意到這個(gè)表示并非量子化假設(shè)。</p><p>　　基于頻率控制字的裝載，NCO在一個(gè)時(shí)期內(nèi)提供一批幅度的輸出值。這個(gè)正弦曲線的頻率域表示在指定的頻率里是一個(gè)推動(dòng)的作用。NCO在NCO參考時(shí)鐘速率下輸出這個(gè)正弦曲線的離

90、散數(shù)字取樣。在時(shí)間域里，NCO輸出是一個(gè)取樣時(shí)鐘邊緣閘門(mén)乘于正弦波形式產(chǎn)生的一個(gè)推動(dòng)序列正弦振幅的作用。在頻率域里，參考時(shí)鐘的取樣產(chǎn)生一系列在K倍的NCO時(shí)鐘頻率脈沖（當(dāng)K=...-1，2，1，2....）。當(dāng)在時(shí)間域里取樣時(shí)鐘乘于正弦曲線，正弦曲線頻率域成分和取樣時(shí)鐘需要卷積來(lái)產(chǎn)生NCO輸出頻率域表示的NCO輸出。</p><p>　　頻率域的結(jié)果是在正弦曲線基本頻率的脈沖作用和別的脈沖作用發(fā)生在K倍的NCO時(shí)

91、鐘頻率加上或減去基本頻率?；镜暮蛣e的成分發(fā)生在：</p><p>　　K*Fclk - Fout</p><p>　　K*Fclk + Fout</p><p>　　當(dāng)K = ... -1, 0 , 1, 2 ..... 和 K = 0是NCO正弦曲線基本頻率。</p><p>　　Fout是指定的NCO正弦曲線輸出頻率</p>

92、<p>　　Fclk是NCO參考時(shí)鐘頻率</p><p>　　DDS系統(tǒng)中的DAC提取NCO的輸出值并轉(zhuǎn)化他們的值為模擬電壓。圖4顯示出時(shí)間和頻率域DAC過(guò)程開(kāi)始于NCO的輸出的表示。DAC輸出是一個(gè)抽樣和保持那些NCO數(shù)字幅度控制字和轉(zhuǎn)換那些值為一個(gè)模擬電壓和保持那些值為一個(gè)抽樣時(shí)鐘周期的電路。DAC過(guò)程的時(shí)域結(jié)構(gòu)是NCO抽樣輸出值和一個(gè)抽樣周期脈沖的卷積。抽樣脈沖的頻率域結(jié)構(gòu)是一個(gè)sin(x)/

93、x功能和在抽樣時(shí)鐘頻率的第一個(gè)零。因?yàn)闀r(shí)域是卷積的，頻率域就是相當(dāng)于相乘。這個(gè)乘法過(guò)程使得NCO輸出有一個(gè)sin(x)/x包絡(luò)。這個(gè)在DAC輸出的衰減在下面計(jì)算出來(lái)而且一個(gè)抽樣輸出頻譜。</p><p>　　Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)]當(dāng)F是輸出頻率， Fclk是抽樣時(shí)鐘頻率&

94、lt;/p><p>　　根據(jù)取樣理論，實(shí)際的值量子化為數(shù)字形式必須考慮一個(gè)DDS系統(tǒng)的性能分析。一個(gè)DDS系統(tǒng)的假的響應(yīng)是主要由兩個(gè)量子化參量確定的。這些參量是相位累加器的相位量子化和ROM正弦曲線表和DAC的量子化量級(jí)。</p><p>　　如上所示，相位累加器只有高Y比特是用來(lái)尋址ROM表。值得注意的是，僅用高Y位引入一個(gè)相位截短。當(dāng)一個(gè)頻率控制字包含一個(gè)非零的值在低（N-Y-1：0）位是

95、裝載到DDS系統(tǒng)的，低非零位累加到高Y位和使得產(chǎn)生一個(gè)相位截短。相位的截短出現(xiàn)的頻率可以根據(jù)以下計(jì)算：</p><p>　　Ftrunc = FW(N-Y-1:0)/2N-Y * Fclk.</p><p>　　一個(gè)相位的截短會(huì)周期性（以Ftrunc速率）相位調(diào)制輸出載波提前2p/28來(lái)補(bǔ)償頻率控制字間隔多于/2Y。相位的跳轉(zhuǎn)由相位截短位累加在基波周?chē)a(chǎn)生突刺。</p>&l

96、t;p>　　這些突刺位于基頻的正和負(fù)截短頻率，突刺的大小是20log(2Y)dBc。一個(gè)相位截短突刺輸出的例子如圖5所示。</p><p>　　在一個(gè)典型的NCO設(shè)計(jì)里，正弦ROM表會(huì)保持一個(gè)1/4正弦波（0，Pi/2）的量級(jí)。ROM表是通過(guò)把所有可能的相位值地址和映射到實(shí)際正弦波大小的近似D比特來(lái)產(chǎn)生的。因此，最大的輸出誤差為?-½ LSB（假設(shè)當(dāng)突刺為-20log(2D)dBc的最壞情況時(shí)）。

97、</p><p>　　類(lèi)似于NCO的ROM表，一個(gè)DAC也同樣是這樣量子化數(shù)字值為模擬值的。一個(gè)DAC輸出的模擬電壓取決于輸入的數(shù)字值。當(dāng)設(shè)計(jì)NCO正弦ROM表時(shí)，一種方法是根據(jù)經(jīng)驗(yàn)好于通過(guò)理解ROM表和DAC之間的交互作用而在DAC線性得出一些數(shù)據(jù)。DAC的量化曲線數(shù)字輸入對(duì)應(yīng)模擬輸出的DAC量化曲線可以看作是理想線性的。微分線性和積分線性這兩個(gè)線性參數(shù)通常是用來(lái)衡量DAC性能。</p><

98、p>　　微分線性是指輸出的步進(jìn)大小為比特到比特。一個(gè)DAC必須編碼一個(gè)最大的1LSB微分線性。當(dāng)輸入碼增加，DAC的輸出必須相應(yīng)增加。假如DAC電壓的增加不是對(duì)應(yīng)于一個(gè)增加的輸入數(shù)字值，可以說(shuō)DAC是缺碼的。因此，一個(gè)有大于1LSB微分線性的10比特DAC可以精確到9或者更小的比特。精確輸出的比特?cái)?shù)量會(huì)導(dǎo)致DDS當(dāng)dl是微分線性的比特?cái)?shù)量時(shí)的虛假的性能-20log(2dl)。</p><p>　　積分線性是

99、一個(gè)DAC的總的線性性能對(duì)一個(gè)理想的線性直線的一個(gè)衡量。那條直線圖當(dāng)DC偏置可能是DAC的最大或者最小時(shí)可以看作“最好的直線”，或者那條直線可以穿過(guò)輸出的最大和最小值的結(jié)束點(diǎn)。超出輸出范圍時(shí)一個(gè)DAC會(huì)有一個(gè)特有的彎曲特性曲線。根據(jù)曲線的形狀和對(duì)稱(chēng)度（半個(gè)DAC輸出的周期對(duì)稱(chēng)），就可以產(chǎn)生DDS基本輸出頻率的輸出“和”。當(dāng)這些“和”接近和超過(guò)Nyquist頻率，F(xiàn)clk/2，這些“和”就成為樣本之下和反映到重要的邊帶，0到Fclk/2。