半導體封裝過程wire bond 中 wire loop 的研究及其優(yōu)化

1、南京師范大學電氣與自動化科學學院畢業(yè)設(shè)計（論文）畢業(yè)設(shè)計（論文）半導體封裝過程半導體封裝過程wirebond中wireloop的研究及其優(yōu)化的研究及其優(yōu)化專業(yè)機電一體化機電一體化班級學號班級學號22010439學生姓名學生姓名劉晶炎劉晶炎單位指導教師單位指導教師儲焱儲焱學校指導教師學校指導教師張朝暉張朝暉評閱教師評閱教師2005年5月30日AbstractDuringtheprocessofthesemiconductassemblyw

2、eusetheAuwiretoconnecttheperipheralcircuitfromtheIC.(ThediameteroftheAuwireisverysmall.Usuallyit’sabout0.8mil~2mil.)duringtheAuwirebondingwecangetdifferentlooptypesfromcontrolthedifferentparameters.Besidesthephysicsacter

3、isticoftheAuwirethelooptypescanalsoaffecttherepellenceundertheoutsidefce.Ftheprocessofthewirebondwehopetherearesomegoodlooptypessothatimprovetherepellenceundertheoutsidefce.Accdingtothisitcanimprovethegooddeviceratioafte

4、rmolding.ItnotonlyreducesthewiresweepingthewireopenofAuwiresbutalsoavoidthebondshtcausebythewiresweeping.Therefewedothedisquisitionaboutthelooptypefgettingthewaytoimprovetherepellenceunderoutsidefces.Thisdisquisitioncans

5、olvetheproblemabout:(1)ImprovetheneckbrokenofAuwire.(2)HeightentheBSTdata.(3)EnhancetheresistfcetoEMCduringthemoldingprocess.(4)Decreasethepossibilityofdevicebrokenwhenitbemoved.Keywd:thesemiconductassemblyAuwirewirebond