外文翻譯---采用高性能的靜態(tài)80c51設(shè)計(jì)的單片機(jī)

1、<p><b>　　附錄III外文資料</b></p><p><b>　　英文文獻(xiàn)</b></p><p>　　The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and er

2、asable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allow

3、s the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip,</p><p><b>　　Features</b>&l

4、t;/p><p>　　* Compatible with MCS-51 Products</p><p>　　* 4K Bytes of In-System Reprogrammable Flash Memory</p><p>　　– Endurance: 1,000 Write/Erase Cycles</p><p>　　* Fully

5、Static Operation: 0 Hz to 24 MHz</p><p>　　* Three-level Program Memory Lock</p><p>　　* 128 x 8-bit Internal RAM</p><p>　　* 32 Programmable I/O Lines</p><p>　　* Two 16-b

6、it Timer/Counters</p><p>　　* Six Interrupt Sources</p><p>　　* Programmable Serial Channel</p><p>　　* Low-power Idle and Power-down Modes</p><p>　　The AT89C51 provides t

7、he following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock cir-cui

8、try. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode</p><p>　　stops the CPU while allowing t

9、he RAM, timer/counters,serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.<

10、/p><p>　　Pin Description</p><p><b>　　VCC</b></p><p>　　Supply voltage.</p><p><b>　　GND</b></p><p><b>　　Ground.</b></p>

11、;<p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can

12、 be used as high-impedance inputs. </p><p>　　Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pu

13、llups.</p><p>　　Port 0 also receives the code bytes during Flash program-</p><p>　　ming, and outputs the code bytes during program verification. External pullups are required during program veri

14、fication.</p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs.When 1s are writ

15、ten to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,</p><p>　　Port 1 pins that are externally being pulled low will source current (I ) because of the interna

16、l pullups. </p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification. </p><p><b>　　Port 2</b></p><p>　　Port 2 is an 8-bit bi-d

17、irectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Por

18、t 2 pins that are externally being pulled low will source current (I ) because of the internal pullups. </p><p>　　Port 2 emits the high-order address byte during fetches from external program memory and duri

19、ng accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @

20、RI), Port 2 emits the contents of the P2 Special Function Register. </p><p>　　Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.</p>&

21、lt;p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they

22、 are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (I ) because of the pullups.</p><p>　　Port 3 also serves the

23、 functions of various special features</p><p>　　of the AT89C51 as listed below:</p><p>　　Port Pin Alternate Functions</p><p>　　P3.0 RXD (serial input port)</p><p>　　P3.

24、1 TXD (serial output port)</p><p>　　P3.2 INT0 (external interrupt 0)</p><p>　　P3.3 INT1 (external interrupt 1)</p><p>　　P3.4 T0 (timer 0 external input)</p><p>　　P3.5 T

25、1 (timer 1 external input)</p><p>　　P3.6 WR (external data memory write strobe)</p><p>　　P3.7 RD (external data memory read strobe)</p><p>　　Port 3 also receives some control signal

26、s for Flash pro-</p><p>　　gramming and verification. </p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles while the oscillator is running

27、 resets the device. </p><p><b>　　ALE/PROG</b></p><p>　　Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also

28、 the program pulse input (PROG) during Flash programming. </p><p>　　In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purp

29、oses. Note, however, that one ALE pulse is skipped during each access to external DataMemory. </p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE i

30、s active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p><b>　　PS

31、EN</b></p><p>　　Program Store Enable is the read strobe to external program memory. </p><p>　　When the AT89C51 is executing code from external program memory, PSEN is activated twice each

32、machine cycle, except that two PSEN activations are skipped during each access to external data memory. </p><p><b>　　EA/VPP</b></p><p>　　External Access Enable. EA must be strapped t

33、o GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.</p><p>　　Note, however, that if lock bit 1 is programmed, EA will beinternally latched

34、on reset.</p><p>　　EA should be strapped to VCC for internal program executions.</p><p>　　This pin also receives the 12-volt programming enable voltage (VPP ) during Flash programming, for parts

35、 that require 12-volt VPP</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting oscillator amplifier and input to the internal clock operating circuit. </p><p><b>

36、　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier. Oscillator Characteristics </p><p>　　XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier w

37、hich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected

38、 while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two f</p><p>　

39、　Idle Mode </p><p>　　In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions

40、registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. </p><p>　　It should be noted that when idle is terminated by a hard ware reset, t

41、he device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access

42、 to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by</p><p>　　reset, the instruction following the one that invokes Idle should not

43、 be one that writes to a port pin or to external memory.</p><p>　　Power-down Mode </p><p>　　In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the

44、last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does

45、not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to </p><p>　　Program Memory Lock

46、 Bits </p><p>　　On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.</p><p>　　When lock bit 1

47、is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is

48、 necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.</p><p>　　Programming the Flash </p><p>　　The AT89C5

49、1 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interfaceaccepts either a high-voltage (12-volt) or a low-voltage (VCC )

50、program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third-party Flash

51、or EPROM programmers.</p><p>　　The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the follow

52、ing table.</p><p>　　The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the

53、Chip Erase Mode.</p><p>　　Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and</p><p>　

54、　Figure 3 and Figure 4. To program the AT89C51, take the following steps.</p><p>　　1. Input the desired memory location on the address lines.</p><p>　　2. Input the appropriate data byte on the d

55、ata lines. </p><p>　　3. Activate the correct combination of control signals.</p><p>　　4. Raise EA/VPP to 12V for the high-voltage programming mode. </p><p>　　5. Pulse ALE/PROG once

56、to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the

57、 end of the object file is reached.</p><p>　　Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result

58、 in the com-</p><p>　　plement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a

59、write cycle has been initiated. </p><p>　　Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate

60、 BUSY. P3.4 is pulled high again when programming is done to indicate READY.</p><p>　　Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the addr

61、ess and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.</p><p>　　Chip Erase: The entire Flash a

62、rray is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code mem

63、ory can be re-programmed. </p><p>　　Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and</p>

64、<p>　　P3.7 must be pulled to a logic low. The values returned are as follows. </p><p>　　(030H) = 1EH indicates manufactured by Atmel</p><p>　　(031H) = 51H indicates 89C51</p><p&

65、gt;　　(032H) = FFH indicates 12V programming</p><p>　　(032H) = 05H indicates 5V programming</p><p>　　Programming Interface</p><p>　　Every code byte in the Flash array can be written

66、and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self-</p><p>　　timed and once initiated, will automatically time itself to completion.

67、</p><p>　　All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.</p><p>&

68、lt;b>　　中文翻譯</b></p><p>　　該系列單片機(jī)是采用高性能的靜態(tài)80C51設(shè)計(jì)。由先進(jìn)CMOS工藝制造并帶有非易失性 Flash 程序存儲器。全部支持12時(shí)鐘6時(shí)鐘操作。 </p><p>　　AT89C51包含128字節(jié)和256字節(jié)RAM 32條I/O口線3個(gè) 16位定時(shí)/計(jì)數(shù)器。 6 輸入4優(yōu)先級嵌套中斷結(jié)構(gòu)1個(gè)串行I/O口，可用于多機(jī)通信I/O擴(kuò)展

69、或全雙工UART以及片內(nèi)振蕩器和時(shí)鐘電路 ，此外，由于器件采用了靜態(tài)設(shè)計(jì)，可提供很寬的操作頻率范圍，頻率可降至0，可實(shí)現(xiàn)兩個(gè)由軟件選擇的節(jié)電模式，空閑模式和掉電模式，空閑模式凍結(jié) CPU，但 RAM，定時(shí)器，串口和中斷系統(tǒng)仍然工作。掉電模式保存RAM的內(nèi)容，但是凍結(jié)振蕩器，導(dǎo)致所有其它的片內(nèi)功能停止工作，由于設(shè)計(jì)是靜態(tài)的，時(shí)鐘可停止而不會丟失用戶數(shù)據(jù)，運(yùn)行可從時(shí)鐘停止處恢復(fù)。 </p><p><b>

70、　　特性 </b></p><p>　　80C51 核心處理單元 </p><p>　　4k字節(jié) FLASH 89C51X2 </p><p><b>　　布爾處理器 </b></p><p>　　全靜態(tài)操作，12時(shí)鐘操作，可選6個(gè)時(shí)鐘 通過軟件或并行編程器，存儲器尋址范圍 </p>&l

71、t;p>　　64K字節(jié)ROM和64K字節(jié)RAM電源控制模式 </p><p>　　―時(shí)鐘可停止和恢復(fù) </p><p><b>　　―空閑模式 </b></p><p><b>　　―掉電模式</b></p><p><b>　　兩個(gè)工作頻率范圍 </b></p&g

72、t;<p>　　6時(shí)鐘模式時(shí)為0到20MHz </p><p>　　12時(shí)鐘模式時(shí)為0到33MHz，LQFP, PLCC或DIP封裝，擴(kuò)展溫度范圍，雙數(shù)據(jù)指針，3個(gè)加密位</p><p>　　4個(gè)中斷優(yōu)先級，6個(gè)中斷源，4個(gè)8位I/O口，全雙工增強(qiáng)型UART </p><p><b>　　―幀數(shù)據(jù)錯誤檢測 </b></p&g

73、t;<p>　　―自動地址識別3個(gè)16位定時(shí)/計(jì)數(shù)器，T0，T1，標(biāo)準(zhǔn)89C51，和增加的T2捕獲和比較，可編程時(shí)鐘輸出，異步端口復(fù)位，低EMI(禁止ALE以及6時(shí)鐘模式) ，掉電模式可通過外部中斷喚醒</p><p><b>　　管腳描述 </b></p><p>　　Vss 地 </p><p>　　Vcc

74、 電源 ，提供掉電， 空閑， 正常工作電壓 </p><p>　　P0.0-0.7 I/OP0口，P0口是開漏雙向口可以寫為1使其狀態(tài)為懸浮用作高阻輸入，P0也可以在訪問外部程序存儲器時(shí)作地址的低字節(jié) 在訪問外部數(shù)據(jù)存儲器時(shí)作數(shù)據(jù)總線，此時(shí)通過內(nèi)部強(qiáng)上拉輸出1</p><p>　　P1.0-1.7 I/OP1口，P1口是帶內(nèi)部上拉的雙向I/O口向P1口寫入11-3時(shí)P1口被內(nèi)部上拉為

75、高電平，可用作輸入口，當(dāng)作為輸入腳時(shí)，被外部拉低的P1口會因?yàn)閮?nèi)部上拉而輸出電流(見 DC 電氣特性)。 </p><p><b>　　P1口第2功能 </b></p><p>　　1 .2 T2(P1.0) ， 定時(shí)/計(jì)數(shù)器2的外部計(jì)數(shù)輸入/時(shí)鐘輸出(見可編程輸出)。</p><p>　　2 .3 T2EX(P1.1) ，定時(shí)/計(jì)數(shù)器2

76、重裝載/捕捉/方向控制。</p><p>　　P2.0-2.7 I/OP2口，P2口是帶內(nèi)部上拉的雙向I/O口，向P2口寫入1時(shí)，P2口被內(nèi)部上拉為高電平，可用作輸入口，當(dāng)作為輸入腳時(shí)，被外部拉低的P2口會因?yàn)閮?nèi)部上拉而輸出電流(見 DC 電氣特性)。在訪問外部程序存儲器和外部數(shù)據(jù)時(shí)分別作為地址高位字節(jié)和 16位地址(MOVX @DPTR)，此時(shí)通過內(nèi)部強(qiáng)上拉傳送1當(dāng)使用8位尋址方式(MOV @Ri)訪問外部數(shù)

77、據(jù)存儲器時(shí),P2口發(fā)送P2 特殊功能寄存器的內(nèi)容。</p><p>　　P3.0-3.7 I/OP3口，P3口是帶內(nèi)部上拉的雙向I/O口，向P3口寫入1時(shí)P3口被內(nèi)部上拉為高電平，可用作輸入口，當(dāng)作為輸入腳時(shí)，被外部拉低的P3口會因?yàn)閮?nèi)部上拉而輸出電流(見 DC 電氣特性)。</p><p>　　P3口還具有以下特殊功能 </p><p>　　10 RxD

78、(p3.0) 串行輸入口 </p><p>　　11 TxD(P3.1) 串行輸出口 </p><p>　　12 INT0(P3.2) 外部中斷0</p><p>　　13 INT1(P3.3) 外部中斷 </p><p>　　14 T0(P3.4) 定時(shí)器0外部輸入 </p>

79、<p>　　15 T1(P3.5) 定時(shí)器1外部輸入 </p><p>　　16 WR(P3.6) 外部數(shù)據(jù)存儲器寫信號 </p><p>　　17 RD(P3.7) 外部數(shù)據(jù)存儲器讀信號 </p><p>　　RST 復(fù)位 </p><p>　　當(dāng)晶振在運(yùn)行中,只要復(fù)位管腳出現(xiàn)2個(gè)機(jī)器周期

80、高電平即可復(fù)位，內(nèi)部有擴(kuò)散電阻連接到Vss僅需要外接一個(gè)電容到Vcc即可實(shí)現(xiàn)上電復(fù)位。</p><p>　　ALE 地址鎖存使能 </p><p>　　在訪問外部存儲器時(shí)，輸出脈沖鎖存地址的低字節(jié)，在正常情況下ALE輸出信號恒定為1/6振蕩頻率，并可用作外部時(shí)鐘或定時(shí)，注意每次訪問外部數(shù)據(jù)時(shí)一個(gè)ALE脈沖將被忽略ALE可以通過置位SFR的。</p><p>　

81、　auxlilary.0 禁止 置位后ALE只能在執(zhí)行MOVX 指令時(shí)被激活。 </p><p>　　PSEN 程序存儲使能 </p><p>　　當(dāng)執(zhí)行外部程序存儲器代碼時(shí)PSEN每個(gè)機(jī)器周期被激活兩次，在訪問外部數(shù)據(jù)存儲器時(shí)PSEN無效，訪問內(nèi)部程序存儲器時(shí)PSEN無效。 </p><p>　　EA/Vpp 外部尋址使能/編程電壓</p>&l

82、t;p>　　在訪問整個(gè)外部程序存儲器時(shí)EA必須外部置低，如果EA為高時(shí)，將執(zhí)行內(nèi)部程序，除非程序計(jì)數(shù)器包含大于片內(nèi)FLASH的地址，該引腳在對FLASH編程時(shí)接5V/12V編程電壓(Vpp)；如果保密1已編程，EA在復(fù)位時(shí)由內(nèi)部鎖存 </p><p>　　XTAL1，晶體1反相振蕩放大器輸入和內(nèi)部時(shí)鐘發(fā)生電路輸入XTAL2，晶體2反相振蕩放大器輸出。</p><p>　　FLASH

83、 EPROM存儲器 </p><p><b>　　概述 </b></p><p>　　P89C51X2/52X2/54X2/58X2在10000次擦除和編程之后仍能可靠保存FLASH存儲器的內(nèi)容，存儲單元的設(shè)計(jì)使得擦除和編程結(jié)構(gòu)最優(yōu)化。此外，先進(jìn)的溝道氧化工藝和低內(nèi)部電場的結(jié)合使擦除和編程操作更加可靠。</p><p><b>　　特

84、性 </b></p><p>　　帶片擦除FLASH EPROM內(nèi)部程序存儲器。內(nèi)部程序存儲器禁止時(shí)，EA=0， 外部程序存儲器最多可達(dá)64K，可編程加密位。每字節(jié)最少10000次擦除/編程周期，數(shù)據(jù)最少可保存10年，從一般銷售商處可獲得編程支持。</p><p><b>　　振蕩器特性 </b></p><p>　　XTAL1和X

85、TAL2為輸入和輸出，可分別作為一個(gè)反相放大器的輸入和輸出 此管腳可配置為使用內(nèi)部振蕩器。要使用外部時(shí)鐘源驅(qū)動器件時(shí)XTAL2可以不連接而由XTAL1驅(qū)動，外部時(shí)鐘信號無占空比的要求，因?yàn)闀r(shí)鐘通過觸發(fā)器二分頻輸入到內(nèi)部時(shí)鐘電路，但高低電平的最長和最短時(shí)間必須符合手冊的規(guī)定。</p><p>　　時(shí)鐘控制寄存器 CKCON </p><p>　　該器件提供通過一個(gè)SFR位CKCON的X2位

86、和一個(gè)Flash位，保密塊中的 FX2控制選擇6時(shí)鐘/12時(shí)鐘模式。當(dāng)X2置0時(shí)。12時(shí)鐘模式有效，該位置1時(shí)系統(tǒng)切換到6時(shí)鐘模式，由于該功能是通過SFR位實(shí)現(xiàn)的，因此可以隨時(shí)訪問并修改，需要注意的是，將X2從0改為1將導(dǎo)致用戶代碼以兩倍的速度執(zhí)行， 因?yàn)樗械南到y(tǒng)時(shí)間間隔都變成原來的 1/2從6時(shí)鐘模式變?yōu)?2時(shí)鐘模式會將運(yùn)行代碼的速度降低為1/2 。</p><p><b>　　可編程時(shí)鐘輸出 &l

87、t;/b></p><p>　　可從P1.0編程輸出50%占空比的時(shí)鐘信號 P1.0 除了作為常規(guī) I/O 口外 還有兩個(gè)可選功能： </p><p>　　1 用于定時(shí)/計(jì)數(shù)器2的外部時(shí)鐘輸入。 </p><p>　　2 使用16MHz操作頻率時(shí)12時(shí)鐘模式下輸出，50%占空比的61Hz~4MHz時(shí)鐘信號6時(shí)鐘模式時(shí)為122Hz~8MHz。</

88、p><p>　　要將定時(shí)/計(jì)數(shù)器2配置為時(shí)鐘發(fā)生器，C/T2(T2CON.1)必須清零，而 T2MOD中的T20E位必須置位，要啟動定時(shí)器2還必須將TR2(T2CON.2)置位。 在時(shí)鐘輸出模式中，定時(shí)器2的翻轉(zhuǎn)將不會產(chǎn)生中斷，這和它作為波特率發(fā)生器時(shí)相似，定時(shí)器 2可同時(shí)作為波特率發(fā)生器和時(shí)鐘發(fā)生器。但需要注意的是，波特率和時(shí)鐘輸出頻率相同。 </p><p><b>　　復(fù)位

89、</b></p><p>　　在振蕩器工作時(shí)，將RST腳保持至少兩個(gè)機(jī)器周期高電平，12時(shí)鐘模式為 24個(gè)振蕩器周期，6時(shí)鐘模式為12振蕩器周期，可實(shí)現(xiàn)復(fù)位。為了保證上電復(fù)位的可靠，RST保持高電平的時(shí)間至少為振蕩器啟動時(shí)間，通常為幾個(gè)毫秒，再加上兩個(gè)機(jī)器周期，復(fù)位后，振蕩器以12時(shí)鐘模式運(yùn)行，當(dāng)已通過并行編程器</p><p>　　設(shè)置為6時(shí)鐘模式時(shí)除外。 </p>

90、;<p><b>　　低功耗模式 </b></p><p><b>　　時(shí)鐘停止模式 </b></p><p>　　靜態(tài)設(shè)計(jì)使時(shí)鐘頻率可以降至0MHz(停止)，當(dāng)振蕩器停振時(shí)，RAM和SFR的值保持不變，該模式允許逐步應(yīng)用并可將時(shí)鐘頻率降至任意值以實(shí)現(xiàn)系統(tǒng)功耗的降低，如要實(shí)現(xiàn)最低功耗則建議使用掉電模式。</p><

91、;p><b>　　空閑模式 </b></p><p>　　空閑模式中 ，CPU進(jìn)入睡眠狀態(tài)，但片內(nèi)的外圍電路仍然保持工作狀態(tài)，正常操作模式的最后一條指令執(zhí)行進(jìn)入空閑模式，空閑模式CPU內(nèi)容，片內(nèi) RAM和所有SFR保持原來的值，任何被使能的中斷，此時(shí)，程序從中斷服務(wù)程序處恢復(fù)并繼續(xù)執(zhí)行，或硬件復(fù)位，與上電復(fù)位使用相同的方式啟動處理器，均可終止空閑模式 </p><

92、p><b>　　掉電模式 </b></p><p>　　為了進(jìn)一步降低功耗通過軟件可實(shí)現(xiàn)掉電模式(見表3)該模式中，振蕩器停振并且在最后一條指令執(zhí)行進(jìn)入掉電模式，降到20V時(shí)片內(nèi)RAM和SFR保持原值，在退出掉電模式之前，Vcc必須升至規(guī)定的最低操作電壓 。</p><p>　　硬件復(fù)位或外部中斷均可結(jié)束掉電模式，硬件復(fù)位使所有的SFR重新設(shè)置 但不改變片內(nèi)RA

93、M的值、外部中斷允許SFR和片內(nèi)RAM都保持原值WUPD AUXR1.3，從掉電喚醒，使能或禁止通過外部中斷喚醒掉電。</p><p>　　WUPD=0 禁止 WUPD=1 使能 </p><p>　　要正確退出掉電模式，在Vcc恢復(fù)到正常操作電壓范圍之后，復(fù)位或外部中斷開始執(zhí)行并且要保持足夠長的時(shí)間(通常小于 10ms )，以使振蕩器重新啟動并穩(wěn)定下來。 </p>

94、<p>　　使用外部中斷退出掉電模式時(shí)，INT0和INT1必須使能且配置為電平觸發(fā) 將管腳電平拉低使振蕩器重新啟動，退出掉電模式后將管腳恢復(fù)為高電平，一旦中斷被響應(yīng)，RETI 之后所執(zhí)行的是進(jìn)入掉電模式指令的后一條指令。</p><p><b>　　設(shè)計(jì)中的注意事項(xiàng) </b></p><p>　　當(dāng)空閑模式被硬件復(fù)位所中止時(shí)，器件在內(nèi)部復(fù)位之前從停止處恢復(fù)程

95、序正常運(yùn)行時(shí)間為2個(gè)機(jī)器周期，這段時(shí)間內(nèi)片內(nèi)硬件禁止對內(nèi)部RAM的訪問，但對I/O口的訪問未被禁止，當(dāng)Idle模式被復(fù)位所中止時(shí)，為了消除可能產(chǎn)生的誤寫操作，應(yīng)用Idle模式指令后的指令不應(yīng)執(zhí)行寫I/O口或?qū)懲獠看鎯ζ鞑僮鳌?</p><p><b>　　ONCE 模式 </b></p><p>　　ONCE(在線仿真)模式實(shí)現(xiàn)了對系統(tǒng)的測試和調(diào)試而不需要將器件從電路

96、中移去，進(jìn)入ONCE模式的條件。</p><p>　　1 當(dāng)器件復(fù)位且PSEN為高電平時(shí)，將ALE置低電平 </p><p>　　2 在RST撤除時(shí)，ALE保持低電平。 </p><p>　　當(dāng)器件處于ONCE模式時(shí)，P0口處于懸浮狀態(tài)，其它I/O口ALE和PSEN為弱上拉，振蕩電路保持工作狀態(tài)，器件處于該模式時(shí)，可用仿真器或測試 CPU 驅(qū)

97、動電路，執(zhí)行正常復(fù)位時(shí)恢復(fù)正常操作。 </p><p>　　定時(shí)器0和1的操作，定時(shí)器0和1定時(shí)和計(jì)數(shù)功能由特殊功能寄存器 TMOD 的控制位C/T進(jìn)行選擇，這兩個(gè)定時(shí)/計(jì)數(shù)器有4種操作模式，通過TMOD的M1和M0選擇，兩個(gè)定時(shí)/計(jì)數(shù)器的模式0 1和02都相同，模式3不同如下所述模式0。</p><p>　　將定時(shí)器設(shè)置成模式0時(shí)類似8048定時(shí)器即8位計(jì)數(shù)器帶32分頻的預(yù)分頻器，圖2所

98、示為模式0工作方式。此模式下，定時(shí)器寄存器配置為13位寄存器，當(dāng)計(jì)數(shù)從全為1翻轉(zhuǎn)為全為0時(shí)，定時(shí)器中斷。</p><p>　　標(biāo)志位 TFn 置位 </p><p>　　當(dāng)TRn=1同時(shí)，GATE=0或INTn=1時(shí)定時(shí)器計(jì)數(shù)置位。GATE時(shí)允許由外部輸入 INTn控制定時(shí)器，這樣可實(shí)現(xiàn)脈寬測量 TRn為TCON寄存器內(nèi)的控制位，該13位寄存器包THn全部8個(gè)位及TLn的低5位，TLn的高

99、3位不定，可將其忽略，置位運(yùn)行標(biāo)志TRn不能清零此寄存器。 </p><p>　　模式0的操作對于定時(shí)器0及定時(shí)器1都是相同的，兩個(gè)不同的 GATE位 TMOD.7 和 TMOD.3 分別分配給定時(shí)器0及定時(shí)器1模式1。</p><p>　　模式1除了使用了THn及TLn全部16位外,其它與模式0相同。</p><p>　　模式2 此模式下定時(shí)器寄存器作為可自動重

100、裝的8位計(jì)數(shù)器TLn如圖4所示 TLn的溢出不僅置位Fn，而且將THn內(nèi)容重新裝入TLn，THn內(nèi)容由軟件預(yù)置，重裝時(shí)THn內(nèi)容不變,模式2的操作對于定時(shí)器0及定時(shí)器1是相同的。 </p><p>　　模式3 在模式3中,定時(shí)器1停止計(jì)數(shù)效果與將TR1設(shè)置為0相同，此模式下定時(shí)器0的TL0及TH0作為兩個(gè)獨(dú)立的8位計(jì)數(shù)器，圖5為模式3時(shí)的定時(shí)器0邏輯TL0占用定時(shí)器0的控制位，C/T，GATE，TR0，INT0