單片機畢業(yè)設計外文翻譯---at89c51 應用說明

1、<p>　　AT89C51 PLAYBACK DEVICE</p><p>　　The features of AT89C51 are: Compatible with MCS-51；4K Bytes of In-System Reprogrammable Flash Memory；1,000 Write/Erase Cycles；Fully Static Operation: 0 Hz to 24 M

2、Hz；Three-level Program Memory Lock；128 x 8-bit Internal RAM；32 Programmable I/O Lines；Two 16-bit Timer/Counters；Six Interrupt Sources；Programmable Serial Channel；Low-power Idle and Power-down Modes。 Description：The

3、AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/c</p><p>　　Pin Description：</p><p>　　VCC：Supply voltage.</p><p>　

4、　GND；Ground.</p><p>　　Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high impe

5、dance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes

6、during Flash programming, and outputs the code bytes during program verification. External pull</p><p>　　Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers ca

7、n sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I

8、IL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p>　　Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullu

9、ps. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being p

10、ulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-b</p>

11、;<p>　　Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pu

12、llups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 a

13、s listed below:</p><p>　　Port 3 also receives some control signals for Flash programming</p><p>　　and verification.</p><p>　　RST：Reset input. A high on this pin for two machine cycl

14、es while</p><p>　　the oscillator is running resets the device.</p><p>　　ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. Th

15、is pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Not

16、e, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR locati</p><p>　　PSEN：Program Store Enable is the read s

17、trobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external d

18、ata memory.</p><p>　　EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however,

19、 that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash pro

20、gramming, for parts that require 12-volt VPP.</p><p>　　XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　XTAL2：Output from the inverti

21、ng oscillator amplifier. </p><p>　　Oscillator Characteristics：XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on chip oscillator, as sh

22、own in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requ

23、irements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry </p><p>　　AT89C51 應用說明</p><p>　　AT89C51的主要性能參數：與MCS-51產品指令系統(tǒng)完全兼容；4k 字節(jié)可重擦寫FLASH閃速存儲器；1

24、000次擦寫周期；全靜態(tài)操作：0Hz—24MHz；三級加密程序存儲器；128×8字節(jié)內部RAM；32個可編程I/O口線；2個16位定時/計數器；6個中斷源；可編程串行URAR通道；低功耗空閑和掉電模式。</p><p>　　功能特性概述：AT89C51提供以下標準功能：4k 字節(jié)FLASH閃速存儲器，128字節(jié)內部RAM，32個I/O口線，2個16位定時/計數器，一個5向量兩級中斷結構，一個全雙工串行通

25、信口，片內振蕩器及時鐘電路。同時，AT89C51降至0Hz的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電工作模式?？臻e方式體制CPU的工作，但允許RAM，定時/計數器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內容，但振蕩器體制工作并禁止其他所有不見工作直到下一個硬件復位。</p><p><b>　　管腳說明： </b></p><p>　　VCC：供電電壓。 &l

26、t;/p><p><b>　　GND：接地。 </b></p><p>　　P0口：P0口為一個8位漏級開路雙向I/O口，每腳可吸收8TTL門電流。當P1口的管腳第一次寫1時，被定義為高阻輸入。P0能夠用于外部程序數據存儲器，它可以被定義為數據/地址的第八位。在FIASH編程時，P0 口作為原碼輸入口，當FIASH進行校驗時，P0輸出原碼，此時P0外部必須被拉高。 <

27、;/p><p>　　P1口：P1口是一個內部提供上拉電阻的8位雙向I/O口，P1口緩沖器能接收輸出4TTL門電流。P1口管腳寫入1后，被內部上拉為高，可用作輸入，P1口被外部下拉為低電平時，將輸出電流，這是由于內部上拉的緣故。在FLASH編程和校驗時，P1口作為第八位地址接收。 </p><p>　　P2口：P2口為一個內部上拉電阻的8位雙向I/O口，P2口緩沖器可接收，輸出4個TTL門電流，

28、當P2口被寫“1”時，其管腳被內部上拉電阻拉高，且作為輸入。并因此作為輸入時，P2口的管腳被外部拉低，將輸出電流。這是由于內部上拉的緣故。P2口當用于外部程序存儲器或16位地址外部數據存儲器進行存取時，P2口輸出地址的高八位。在給出地址“1”時，它利用內部上拉優(yōu)勢，當對外部八位地址數據存儲器進行讀寫時，P2口輸出其特殊功能寄存器的內容。P2口在FLASH編程和校驗時接收高八位地址信號和控制信號。 </p><p>

29、;　　P3口：P3口管腳是8個帶內部上拉電阻的雙向I/O口，可接收輸出4個TTL門電流。當P3口寫入“1”后，它們被內部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流（ILL）這是由于上拉的緣故。 </p><p>　　P3口也可作為AT89C51的一些特殊功能口，如下表所示： </p><p>　　P3口同時為閃爍編程和編程校驗接收一些控制信號。 </p

30、><p>　　RST：復位輸入。當振蕩器復位器件時，要保持RST腳兩個機器周期的高電平時間。 </p><p>　　ALE/PROG：當訪問外部存儲器時，地址鎖存允許的輸出電平用于鎖存地址的地位字節(jié)。在FLASH編程期間，此引腳用于輸入編程脈沖。在平時，ALE端以不變的頻率周期輸出正脈沖信號，此頻率為振蕩器頻率的1/6。因此它可用作對外部輸出的脈沖或用于定時目的。然而要注意的是：每當用作外部數

31、據存儲器時，將跳過一個ALE脈沖。如想禁止ALE的輸出可在SFR8EH地址上置0。此時， ALE只有在執(zhí)行MOVX，MOVC指令是ALE才起作用。另外，該引腳被略微拉高。如果微處理器在外部執(zhí)行狀態(tài)ALE禁止，置位無效。 </p><p>　　PSEN：外部程序存儲器的選通信號。在由外部程序存儲器取指期間，每個機器周期兩次/PSEN有效。但在訪問外部數據存儲器時，這兩次有效的/PSEN信號將不出現(xiàn)。 </p&

32、gt;<p>　　EA/VPP：當/EA保持低電平時，則在此期間外部程序存儲器（0000H-FFFFH），不管是否有內部程序存儲器。注意加密方式1時，/EA將內部鎖定為RESET；當/EA端保持高電平時，此間內部程序存儲器。在FLASH編程期間，此引腳也用于施加12V編程電源（VPP）。 </p><p>　　XTAL1：反向振蕩放大器的輸入及內部時鐘工作電路的輸入。 </p><

33、;p>　　XTAL2：來自反向振蕩器的輸出。 </p><p><b>　　振蕩器特性: </b></p><p>　　XTAL1和XTAL2分別為反向放大器的輸入和輸出。該反向放大器可以配置為片內振蕩器。石晶振蕩和陶瓷振蕩均可采用。如采用外部時鐘源驅動器件，XTAL2應不接。有余輸入至內部時鐘信號要通過一個二分頻觸發(fā)器，因此對外部時鐘信號的脈寬無任何要求，但必