通用異步接收發(fā)送器外文翻譯

1、<p><b>　　外文資料原文</b></p><p>　　Transmitting and receiving serial data</p><p>　　The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial

2、 communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.Serial transmis

3、sion of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert th</p><p>　　The UART usually

4、does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external

5、 signaling levels.</p><p>　　External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, the presence or absence of c

6、urrent (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP)

7、. Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are mod</p><p>　　Communication may be "full duplex" (both send and receive at the same time) or "h

8、alf duplex" (devices take turns transmitting and receiving).</p><p>　　As of 2008, UARTs are commonly used with RS-232 for embedded systems communications. It is useful to communicate between microcontro

9、llers and also with PCs. Many chips provide UART functionality in silicon, and low-cost chips exist to convert logic level signals (such as TTL voltages) to RS-232 level signals (for example, Maxim's MAX232).</p&g

10、t;<p>　　Asynchronous receive and transmit</p><p>　　In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to </p><p>　　eight data bits, least-significant-bi

11、t first, an optional "parity" bit, and then one, one and a half, or two "stop" bits. The start bit is the opposite polarity of the data-line's idle state. The stop bit is the data-line's idle

12、state, and provides a delay before the next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the "stop" bit was often stretched to two bit times to give the m

13、echanism more time to finish printing a character. A stretche</p><p>　　The parity bit can either make the number of "one" bits between any start/stop pair odd, or even, or it can be omitted. Odd pa

14、rity is more reliable because it assures that there will always be at least one data transition, and this permits many UARTs to resynchronize.</p><p>　　In synchronous transmission, the clock data is recovere

15、d separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An asynchronous

16、transmission sends no characters over the interconnection when the transmitting device has nothing to send -- only idle stop bits; but a synchronous interface must send "pad" characters to maintain synchronism

17、between the rec</p><p>　　USART chips have both synchronous and asynchronous modes.</p><p>　　Serial to Parallel Algorithm</p><p>　　Asynchronous transmission allows data to be transmi

18、tted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the

19、 sending and receiving units.</p><p>　　When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted

20、. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enou

21、gh to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word. (This requi</p><p>　　After the Start Bit, the individual bits of the word of data are sent, with

22、 the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted </p><p>　　for exactly the same amount of time as all of the other bits, and the receiver “l(fā)ooks” at the wire at

23、approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 o

24、r a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on.</p><p>　　The sender does not know when the receiver has “l(fā)ooked” at the value of the bi

25、t. The sender only knows when the clock says to begin transmitting the next bit of the word.</p><p>　　When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter genera

26、tes. The Parity Bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is sent by the transmitter.</p><p>　　When the receiver has received all of the bits in the data wo

27、rd, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UA

28、RT considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at &

29、lt;/p><p>　　Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are n

30、ot passed to the host. If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent. Because asynchronous data is “self synchronizing”,

31、 if there is no data to transmit, the transmission line can be idle. A data commun</p><p>　　Figure 1 shows this format.</p><p>　　The start bit is always a 0 (logic low), which is also called a s

32、pace. The start bit signals the receiving DTE that a character code is coming. The next five to eight bits, depending on the code set employed, represent the character. In the ASCII code set the eighth data bit may be a

33、parity bit. The next one or two bits are always in the </p><p>　　mark (logic high, i.e., '1') condition and called the stop bit(s). They provide a "rest" interval for the receiving DTE so t

34、hat it may prepare for the next character which may be after the stop bit(s). The rest interval was required by mechanical Teletypes which used a motor driven camshaft to decode each character. At the end of each charact

35、er the motor needed time to strike the character bail (print the character) and reset the camshaft.</p><p>　　All operations of the UART hardware are controlled by a clock signal which runs at a multiple (say

36、, 16) of the data rate - each data bit is as long as 16 clock pulses. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts a

37、t least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line</p><p>　　Transmission op

38、eration is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register, the UART hardware generates a start bit, shifts the required number of data bits out to the

39、 line,generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so

40、that the host system does not deposit a new c</p><p>　　Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART ma

41、y detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the

42、host system.</p><p>　　Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII </p><p>　

43、　character per seconds equals the bit rate divided by 10.</p><p><b>　　History</b></p><p>　　Some early telegraph schemes used variable-length pulses (as in Morse code) and rotating cl

44、ockwork mechanisms to transmit alphabetic characters. The first UART-like devices (with fixed-length pulses) were rotating mechanical switches (commutators). These sent 5-bit Baudot codes for mechanical teletypewriters,

45、and replaced morse code. Later, ASCII required a seven bit code. When IBM built computers in the early 1960s with 8-bit characters, it became customary to store the ASCII code in 8 bits.</p><p>　　Gordon Bell

46、 designed the UART for the PDP series of computers. Western Digital made the first single-chip UART WD1402A around 1971; this was an early example of a medium scale integrated circuit.</p><p>　　An example of

47、 an early 1980s UART was the National Semiconductor 8250. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attent

48、ion from the computer. For example, the popular National Semiconductor 16550 has a 16 byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750, and 16C850.</p><p>　　Depending on the manufac

49、turer, different terms are used to identify devices that perform the UART functions. Intel called their 8251 device a "Programmable Communication Interface". MOS Technology 6551 was known under the name "A

50、synchronous Communications Interface Adapter" (ACIA). The term "Serial Communications Interface" (SCI) was first used at Motorola around 1975 to refer to their start-stop asynchronous serial interface devi

51、ce, which others were calling a UART.</p><p>　　Some very low-cost home computers or embedded systems dispensed with a UART and used the CPU to sample the state of an input port or directly manipulate an

52、output port for data transmission. While very CPU-intensive, since the CPU timing was critical, these schemes avoided the purchase of a costly UART chip. The technique was known as a bit-banging serial port.</p>&

53、lt;p>　　UART models</p><p>　　8250, 16450, early 16550: Obsolete with 1-byte buffers</p><p>　　16550, 16550A, 16C552: 16-byte buffers, TL=1,4,8,14; 115.2 kbps standard, many support 230.4 or 460

54、.8 kbps</p><p>　　16650: 32-byte buffers. 460.8 kbps</p><p>　　16750: 64-byte buffer for send, 56-byte for receive. 921.6 kbps</p><p>　　16850, 16C850: 128-byte buffers. 460.8 kbps or

55、1.5 mbps</p><p>　　16950 Hayes ESP: 1k-byte buffers.</p><p><b>　　Structure</b></p><p>　　A UART usually contains the following components: a clock generator, usually a

56、 multiple of the bit rate to allow sampling in the middle of a bit period.</p><p>　　input and output shift registers</p><p>　　transmit/receive control</p><p>　　read/write control lo

57、gic</p><p>　　transmit/receive buffers (optional)</p><p>　　parallel data bus buffer (optional)</p><p>　　First-in, first-out (FIFO) buffer memory (optional)</p><p>　　Spec

58、ial Receiver Conditions</p><p>　　Overrun Error</p><p>　　An "overrun error" occurs when the UART receiver cannot process the character that just came in before the next one arrives. Var

59、ious UART devices have differing amounts of buffer space to hold received characters. The CPU must service the UART in order to remove characters from the input buffer. If the CPU does not service the UART quickly enough

60、 and the buffer becomes full, an Overrun Error will occur.</p><p>　　Underrun Error</p><p>　　An "underrun error" occurs when the UART transmitter has completed sending a character and t

61、he transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. This error indication is commo

62、nly found in USARTs, since an underrun is more serious in synchronous systems.</p><p>　　Framing Error</p><p>　　A "framing error" occurs when the designated "start" and "

63、stop" bits are not valid. As the "start" bit is used to identify the beginning of an incoming character, itacts as a reference for the remaining bits. If the data line is not in the expected idle state whe

64、n the "stop" bit is expected, a Framing Error will occur.</p><p>　　Parity Error</p><p>　　A "parity error" occurs when the number of "active" bits does not agree wit

65、h the specified parity configuration of the UART, producing a Parity Error. Because the "parity" bit is optional, this error will not occur if parity has been disabled. Parity error is set when the parity of an

66、 incoming data character does not match the expected value.</p><p>　　Break Condition</p><p>　　A "break condition" occurs when the receiver input is at the "space" level for l

67、onger than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error.</p><p>　　Some

68、equipment will deliberately transmit the "break" level for longer than a character as an out-of-band signal. When signaling rates are mismatched, no meaningful characters can be sent, but a long "break&quo

69、t; signal can be a useful way to get the attention of a mismatched receiver to do something (such as resetting itself). UNIX systems and UNIX-like systems such as Linux can use the long "break" level as a reque

70、st to change the signaling rate.</p><p><b>　　Baudrate </b></p><p>　　In embedded designs, it is necessary to choose proper oscillator to get correct baud rate with small or no error.

71、Some examples of common crystal frequencies and baud rates with no error:</p><p>　　18.432 MHz: 300, 600, 1200, 2400, 4800, 9600, 19200 Bd</p><p>　　22.118400 MHz: 300, 600, 1200, 1800, 2400, 4800

72、, 7200, 9600, 14400, 19200, 38400, 57600, 115200 Bd</p><p>　　16 MHz: 125000, 500000 Bd</p><p><b>　　See also</b></p><p>　　Asynchronous serial communication</p><

73、;p><b>　　Baud</b></p><p><b>　　bit rate</b></p><p><b>　　Modem</b></p><p>　　Morse code</p><p>　　Serial communication</p>&l

74、t;p>　　Serial port</p><p><b>　　USB</b></p><p>　　16550 UART</p><p><b>　　8250 UART</b></p><p>　　External links</p><p>　　A tutorial

75、on the RS-232 standard, describing the definition of mark, space and their relationship with negative and positive voltages</p><p>　　Freebsd Tutorials (includes standard signal definitions, history of UART I

76、Cs, and pinout for commonly used DB25 connector)</p><p>　　UART Tutorial for Robotics (contains many practical examples)</p><p><b>　　譯文</b></p><p>　　通用異步接收/發(fā)送器 是一種“異步接收器/

77、發(fā)射器” ，一塊電腦 硬件的轉(zhuǎn)換之間的數(shù)據(jù)并行和串行的形式。UART常用與其他通信標(biāo)準(zhǔn)，如環(huán)境影響評(píng)估 RS - 232接口 。</p><p>　　UART通常是個(gè)（或部分） 積體電路用于串行通訊 ，電腦或外圍設(shè)備的串行端口 。 UART現(xiàn)在包含在微控制器。 雙UART或兩個(gè)UART 杜阿爾特結(jié)合到一個(gè)單一芯片中。 許多現(xiàn)代集成電路與現(xiàn)在的UART還可以溝通同步;這些設(shè)備被稱為通用同步 。 </p>

78、<p>　　Transmitting and receiving serial data 發(fā)送和接收串行數(shù)據(jù)</p><p>　　在通用異步接收/發(fā)送器（ UART接口）控制器是關(guān)鍵的組成部分，串行通信子系統(tǒng)的一臺(tái)計(jì)算機(jī)。 采取的異步字節(jié)的數(shù)據(jù)傳輸和個(gè)人位依次時(shí)尚。 在目的地，第二個(gè)UART重新組裝成完整的bytes.Serial位數(shù)字信息傳輸模式（ bits ）通過一個(gè)單一的有線或其他媒介更符合成

79、本效益比并行傳輸，通過多條線路。阿的UART是用來(lái)轉(zhuǎn)換之間的信息傳播其順序和并行形式兩端的鏈接。 每個(gè)UART接口包含一個(gè)移位寄存器這是最根本的方法之間的轉(zhuǎn)換串行和并行的形式。</p><p>　　該個(gè)UART通常并不直接產(chǎn)生或接收外部信號(hào)之間使用不同的設(shè)備。通常情況下，單獨(dú)的接口設(shè)備是用來(lái)轉(zhuǎn)換邏輯電平信號(hào)的UART和來(lái)自外部信號(hào)的水平。</p><p>　　外部信號(hào)可能有許多不同的形式。

80、 實(shí)例標(biāo)準(zhǔn)電壓信號(hào)的RS - 232接口 ， 遙感- 422和RS - 485接口的環(huán)境影響評(píng)估 。從歷史上看，存在或不存在電流（在目前的循環(huán) ）用于電報(bào)電路。 一些信令計(jì)劃不使用電線。.例如是光纖 ，支持IrDA （ 紅外 ）和（無(wú)線） 藍(lán)牙在串口簡(jiǎn)介（許可證） 。 一些計(jì)劃使用信號(hào)調(diào)制的載波信號(hào)（帶或不帶線） 。例子有調(diào)制的音頻信號(hào)與電話線調(diào)制解調(diào)器 ，射頻調(diào)制數(shù)據(jù)收音機(jī)，以及直流林的電力線載波通信 。</p><

81、;p>　　通信可能是“全雙工” （發(fā)送和接收在同一時(shí)間）或“半雙工” （設(shè)備輪流發(fā)送和接收） 。</p><p>　　截至2008年，個(gè)UART常用的RS - 232接口的嵌入式系統(tǒng)的通信。 它是有用的微控制器之間的溝通，并與個(gè)人電腦。 許多芯片提供的UART功能硅，和低成本的芯片存在轉(zhuǎn)換邏輯電平信號(hào)（如對(duì)焦TTL電壓） ，以RS - 232接口信號(hào)（例如， Maxim的MAX232 ） 。</p&g

82、t;<p>　　Asynchronous receive and transmit 異步接收和發(fā)送</p><p>　　在異步傳輸， 電傳式個(gè)UART發(fā)送“開始”位， 7點(diǎn)55比特的數(shù)據(jù)，最重要的位第一，一個(gè)可選的“平價(jià)”位，然后一，一個(gè)半或兩個(gè)“一站式”的位。 起始位是極性相反的數(shù)據(jù)線的空閑狀態(tài)。 停車位是數(shù)據(jù)線的空閑狀態(tài)，并規(guī)定在一段時(shí)間后，下一個(gè)字符就可以開始。 （這就是所謂的異步起止傳輸）

83、 。在機(jī)械teletypes的“一站式”位往往延伸到2位，以使這一機(jī)制更多的時(shí)間來(lái)完成印刷字符。加長(zhǎng)“一站式”位也有助于同步。</p><p>　　奇偶校驗(yàn)位可以使一些“一”位之間的任何啟動(dòng)/停止對(duì)奇怪的，甚至，也可以省略。奇數(shù)奇偶更可靠，因?yàn)樗_保總是會(huì)有至少一個(gè)數(shù)據(jù)過渡，這許多個(gè)UART ，以允許同步。</p><p>　　在同步傳輸，時(shí)鐘數(shù)據(jù)恢復(fù)分開的數(shù)據(jù)流，并沒有啟動(dòng)/停止位被使用

84、。這提高了效率，傳輸?shù)倪m當(dāng)渠道，因?yàn)楦嗟谋忍匕l(fā)出的可用的數(shù)據(jù)，而不是性質(zhì)的框架。異步傳輸傳送任何字符的互連時(shí)，傳動(dòng)裝置無(wú)關(guān)發(fā)送-只有閑置停止位;但同步接口必須發(fā)出“墊”字符之間保持同步的接收器和發(fā)射器。 通常的填料是ASCII的 “同步”的特點(diǎn)。 這可能是自動(dòng)完成的傳動(dòng)裝置。</p><p>　　芯片同步和異步模式。</p><p>　　Serial to Parallel Algori

85、thm 串行到并行算法</p><p>　　異步傳輸允許數(shù)據(jù)傳送有沒有發(fā)件人發(fā)送時(shí)鐘信號(hào)的接收器。相反，發(fā)送和接收必須商定時(shí)間提前參數(shù)和特殊位被添加到每個(gè)單詞用來(lái)同步發(fā)送和接收單位。</p><p>　　如果某個(gè)詞給予的UART異步傳輸，有些所謂的“開始有點(diǎn)”被添加到開始每個(gè)單詞是將轉(zhuǎn)交。 起始位是用來(lái)提醒接收器，一個(gè)字的數(shù)據(jù)即將發(fā)出，并以武力的時(shí)鐘同步接收到的時(shí)鐘發(fā)射機(jī)。 這兩個(gè)時(shí)鐘必須

86、準(zhǔn)確沒有足夠的頻率漂移了10 ％以上的傳輸過程中的其余位在Word 。 （此要求是在未來(lái)的日子機(jī)械電傳打字電報(bào)，是很容易滿足了現(xiàn)代化的電子設(shè)備。 ）開始后位，個(gè)人位的話，數(shù)據(jù)傳送，以最低有效位（ LSB的）被第一次。每比特的傳輸轉(zhuǎn)交正是相同的時(shí)間內(nèi)為所有其他位，并接收“期待”在鐵絲網(wǎng)約一半的期間分配給每個(gè)位，以決定是否位是1或0 。 例如，如果需要兩秒鐘發(fā)送每比特，將審查接收的信號(hào)以確定它是否是一個(gè)1或0后一秒過去了，然后將等待2秒鐘，

87、然后檢查的價(jià)值，未來(lái)位等等。</p><p>　　.發(fā)件人不知道什么時(shí)候接收了“期待”的價(jià)值位。 寄件人只知道說，當(dāng)時(shí)鐘開始轉(zhuǎn)遞明年位一詞。</p><p>　　.當(dāng)整個(gè)數(shù)據(jù)一詞已發(fā)送，發(fā)射器可添加一個(gè)奇偶校驗(yàn)位產(chǎn)生的發(fā)射機(jī)。 的奇偶校驗(yàn)位可使用的接收器進(jìn)行簡(jiǎn)單的錯(cuò)誤檢查。那么至少一站式位發(fā)射機(jī)發(fā)出的。</p><p>　　當(dāng)接收器收到的所有比特的數(shù)據(jù)字，可以檢查奇

88、偶校驗(yàn)碼（包括發(fā)送和接收必須商定是否有奇偶校驗(yàn)位將用于） ，然后接收尋找停止位。 如果停止位時(shí)，沒有出現(xiàn)這是理應(yīng)的異步認(rèn)為整個(gè)詞是亂碼，并將報(bào)告幀錯(cuò)誤的主機(jī)處理器的數(shù)據(jù)時(shí)，讀字。 通常的原因幀錯(cuò)誤的是，發(fā)送和接收時(shí)鐘并沒有運(yùn)行在相同的速度，或者說，信號(hào)中斷。</p><p>　　無(wú)論是收到的數(shù)據(jù)正確與否，自動(dòng)丟棄的UART開始，奇偶校驗(yàn)和停止位。 如果發(fā)送和接收的配置相同，這些位不能傳遞到主機(jī)。如果另一個(gè)詞準(zhǔn)備傳

89、輸，開始位的新詞可以發(fā)送盡快停止位前一詞已發(fā)送。 由于異步數(shù)據(jù)是“自我同步” ，如果沒有數(shù)據(jù)傳輸，傳輸線可以閑置。阿數(shù)據(jù)通信 脈沖只能在兩個(gè)國(guó)家之一，但也有許多名字，這兩個(gè)國(guó)家。 當(dāng)打開時(shí)，關(guān)閉電路，低電壓，電流流動(dòng)，或邏輯為零，脈搏據(jù)說是在“空間”的條件。如果是off ，電路開放式，高電壓，電流停止，或邏輯1 ，脈沖被認(rèn)為是在“商標(biāo)”的條件。 阿字符代碼始于數(shù)據(jù)通信電路在空間條件。 如果該商標(biāo)的條件看來(lái)，是一個(gè)合乎邏輯的一個(gè)合乎邏輯的

90、記錄，否則為零。</p><p>　　開始位總是0 （邏輯低） ，也就是所謂的空間 。 起始位信號(hào)接收終端的字符代碼正在到來(lái)。在今后的5到8位，這取決于代碼集就業(yè)，代表的性質(zhì)。在ASCII碼的數(shù)據(jù)集第八位可能是奇偶校驗(yàn)位。在未來(lái)一個(gè)或兩個(gè)位都是在馬克 （邏輯高，也就是說， '1 ' ）的條件，并呼吁停止位（縣） 。他們提供了一個(gè)“休息”間隔接收終端 ，以便它可以準(zhǔn)備下一個(gè)字符可能會(huì)在停止位（縣）

91、。 其余的時(shí)間間隔，需要用機(jī)械Teletypes使用電動(dòng)機(jī)驅(qū)動(dòng)凸輪軸解碼每個(gè)字符。 在每個(gè)字符的運(yùn)動(dòng)需要更多的時(shí)間來(lái)打擊性質(zhì)保釋（打印的字符）和重置凸輪軸。</p><p>　　所有業(yè)務(wù)的UART硬件控制的時(shí)鐘信號(hào)運(yùn)行在一個(gè)多（也就是說， 16日）的數(shù)據(jù)速率-每個(gè)數(shù)據(jù)位是，只要16個(gè)時(shí)鐘脈沖。 T該接收機(jī)測(cè)試狀態(tài)的輸入信號(hào)在每個(gè)時(shí)鐘脈沖，尋找開始啟動(dòng)位。如果明顯開始位持續(xù)至少有一半的比特時(shí)間，它是有效的，信號(hào)開始

92、一個(gè)新的特點(diǎn)。 如果不是，虛偽的脈沖被忽略。 等待進(jìn)一步位時(shí)間，國(guó)家線再次取樣和由此產(chǎn)生的水平頻率為移位寄存器。 后所需數(shù)目的位期間的字符長(zhǎng)度（第5至第8位，通常）已經(jīng)過去了，內(nèi)容的移位寄存器是提供（并行方式）的接收系統(tǒng)。 該個(gè)UART將國(guó)旗表明新的數(shù)據(jù)，而且還可能產(chǎn)生一個(gè)處理器的中斷請(qǐng)求，主機(jī)處理器轉(zhuǎn)讓收到的數(shù)據(jù)。在一些常見的</p><p>　　UART ，一個(gè)小頭中，先出（ FIFO的）緩沖存儲(chǔ)器之間插入接

93、收移位寄存器和主機(jī)系統(tǒng)的接口。 這使得主處理器有更多的時(shí)間來(lái)處理中斷的UART和防止損失收到的數(shù)據(jù)率高。</p><p>　　system.傳輸操作更簡(jiǎn)單，因?yàn)樗刂葡碌膫鬏斚到y(tǒng)。當(dāng)數(shù)據(jù)保存在移位寄存器的硬件生成的UART開始位，轉(zhuǎn)變所需數(shù)量的數(shù)據(jù)位到線，生成和附加的奇偶校驗(yàn)位（如果使用） ，以及附加的停止位。 由于傳輸?shù)囊粋€(gè)單一的字符可能會(huì)需要很長(zhǎng)的時(shí)間相對(duì)于CPU的速度，將保持的UART國(guó)旗顯示繁忙的地位，讓

94、主機(jī)系統(tǒng)并不存款一個(gè)新的字符傳輸?shù)角耙粋€(gè)已經(jīng)完成，這也可能是完成中斷。自全雙工操作需要的字符將發(fā)送和接收在同一時(shí)間，實(shí)際個(gè)UART使用兩種不同的移位寄存器的傳播特征及收到字符。</p><p>　　發(fā)送和接收UART接口必須設(shè)置為同一位速度，字符長(zhǎng)度，奇偶校驗(yàn)，停止位的正常運(yùn)行。 接收的UART可以檢測(cè)一些不相符的設(shè)置，并設(shè)定了“幀錯(cuò)誤”標(biāo)志位的主機(jī)系統(tǒng);在特殊情況下，接收的UART將產(chǎn)生不穩(wěn)定流肢解字符和他們轉(zhuǎn)

95、移到主機(jī)系統(tǒng)。.典型的串行端口，使用個(gè)人電腦連接到調(diào)制解調(diào)器使用了8個(gè)數(shù)據(jù)位，無(wú)奇偶校驗(yàn)，一個(gè)停止位;這一配置的數(shù)量ASCII字符每秒等于比特率除以10 。</p><p>　　History 歷史</p><p>　　有些早期的電報(bào)計(jì)劃使用可變長(zhǎng)度豆類（如在莫爾斯電碼 ）和旋轉(zhuǎn)發(fā)條機(jī)制轉(zhuǎn)交字母。第一次的UART樣裝置（與固定長(zhǎng)度脈沖）的旋轉(zhuǎn)機(jī)械式開關(guān)（ 換向器 ） 。這些派出5位Bau

96、dot教授守則機(jī)械teletypewriters ，取代莫爾斯電碼 。 Later, ASCII required a seven bit code.后來(lái)， ASCII的需要7位代碼。當(dāng)IBM公司建立的計(jì)算機(jī)在60年代初的8位字符，它成為習(xí)慣存儲(chǔ)ASCII碼的8位。</p><p>　　貝爾的UART設(shè)計(jì)的等離子系列個(gè)人電腦。 西部數(shù)字作出了第一款單芯片的UART WD1402A約1971年;這是一個(gè)早期的例子一

97、個(gè)中等規(guī)模的集成電路 。</p><p>　　一個(gè)例子是20世紀(jì)80年代初的UART是美國(guó)國(guó)家半導(dǎo)體 8250 。在20世紀(jì)90年代，制定了新的UART接口，帶有片上緩沖器。這使得傳輸速度更高的數(shù)據(jù)丟失和未經(jīng)而不需要如此頻繁的注意力從電腦。例如，流行的國(guó)家半導(dǎo)體16550有一個(gè)16字節(jié)的FIFO ，并產(chǎn)生許多變種，其中包括16C550 ， 16C650 ， 16C750和16C850 。</p>&

98、lt;p>　　根據(jù)不同的制造商，不同的條件下可用于識(shí)別裝置執(zhí)行的UART功能。 英特爾所謂的8251設(shè)備的“可編程通信接口” 。 馬鞍山技術(shù) 6551已知的名義下“異步通信接口適配器” （ ACIA ） 。 所謂“串行通信接口” （ SCI ）的首次使用在摩托羅拉公司在1975年提及的起止異步串行接口設(shè)備，它被調(diào)用的</p><p><b>　　UART 。</b></p>

99、<p>　　一些成本很低的家庭計(jì)算機(jī)或嵌入式系統(tǒng)配有UART和使用的CPU樣品狀況的一個(gè)輸入端口，或直接操縱輸出端口的數(shù)據(jù)傳輸。雖然非常CPU密集型的，因?yàn)镃PU的時(shí)間是至關(guān)重要的，這些計(jì)劃避免了購(gòu)買昂貴的UART芯片。 這項(xiàng)技術(shù)被稱為位撞串行端口。</p><p>　　UART models 異步模式</p><p>　　早期16550 ：過時(shí)1字節(jié)緩沖器</p&g

100、t;<p>　　1 16字節(jié)緩沖器的TL = 1,4,8,14 ; 115.2 kbps的標(biāo)準(zhǔn)，許多支持230.4或460.8 kbps的</p><p>　　32字節(jié)的緩沖區(qū)。 460.8 kbps 460.8 kbps的</p><p>　　64字節(jié)的緩沖區(qū)發(fā)送， 56字節(jié)的接收。 921.6 kbps 921.6 kbps的</p><p>　　

101、128字節(jié)的緩沖區(qū)。 460.8 kbps or 1.5 mbps 460.8 Kbps或1.5 Mbps的</p><p>　　16950 16950</p><p>　　Hayes ESP: 1k-byte buffers. 1000字節(jié)的緩沖區(qū)。</p><p>　　Structure 結(jié)構(gòu)</p><p>　　UART通常包含以下內(nèi)容

102、：</p><p>　　.時(shí)鐘發(fā)生器，通常是多種的比特率，使樣品中有點(diǎn)時(shí)期。</p><p>　　輸入和輸出移位寄存器</p><p><b>　　發(fā)射/接收控制</b></p><p><b>　　讀/寫控制邏輯</b></p><p>　　發(fā)射/接收緩沖器（可選）<