高性能嵌入式同步SRAM的研究與設(shè)計.pdf

1、復(fù)旦大學(xué)碩士學(xué)位論文高性能嵌入式同步SRAM的研究與設(shè)計姓名：曹妙申請學(xué)位級別：碩士專業(yè)：電子與通信工程指導(dǎo)教師：洪志良20091008AbstractSRAM，whichhasbecomeacriticalcomponentofmodemVLSI，hasattractedmuchmoreattentionrecentlyThispapermalnlyfocusesonhowtodesignahigllperformanceSRAMAf

2、tertheresearchofSRAMcellsandperipherycircuits，wetrytofindawaytoacceleratethereadandwriteoperationspeed，andreducethepowerdissipationThispaperfirstintroducestheprincipleofhowtodecideSRAMarraysizeItshowsthatlargearraysizelo

3、wersspeedandincreasespowerdissipationwhilesmallarraysizeincreaseschipcostsWordlinedecoderinfluencesthedelayfromclocktowordlinedirectlySOit’SnecessarytodesignahighspeedwordlinedecoderInVDSMprocess，interconnect&layisdomina

4、ntWordlineresistancecanbedecreasedbyenlargingthewidthofwordlinemetalThus，thewordlinespeedisacceleratedandthepowerisreducedAlso，bitlinecapacitancescanbereducedbyreducingthewidthofbitlinemetal，SOthechargesinthebitlinewillb

5、edischargedquicklyTheuseofprechargecircuitsandsenseamplifiercircuitsgreatlyacceleratesthereadspeedVoltagelatchedsenseamplifierispopularbecauseofitssmallareafastspeedandllighsensitivityThispaperreportsthedesignof64KbSRAM、

6、析tllCMOSsixtransistorSRAMcellItuses65nmCMOSNwellprocesswinlonepolyandfivelevelmetalsAfterpostlayoutsimulation，itshowsthat，whenatSScomerand125“(2，麗tllasupplyvoltageof09vthetimefromthehighedgeofclocktothedataoutputsignal一R