基于quartusii以及74ls192為核心的簡易數(shù)字時鐘設(shè)計

1、基于 基于 QuartusII 以及 以及 74ls192 為核 為核心的簡易數(shù)字時鐘設(shè)計 心的簡易數(shù)字時鐘設(shè)計該項目是利用 QuartusII 軟件設(shè)計一個數(shù)字鐘，進行試驗設(shè)計和仿真調(diào)試，實現(xiàn)了計時，校時，校分，保持和整點報時功能，并下載到 FPGA 實驗系統(tǒng)中進行調(diào)試和驗證。此外還添加了顯示星期，使得設(shè)計的數(shù)字鐘的功能更加完善。關(guān)鍵字：QuartusII EDA FPGA 數(shù)字鐘 74ls192 This This experi

2、ment experiment is is to to design design a digital digital clock clock using using QuartusII QuartusII software, software, debugging debugging test test design design and and simulation, simulation, to to achieve ac

3、hieve timing, timing, timing, timing, school school hours, hours, maintain maintain and and the the whole whole point point timekeeping timekeeping function, function, and and download download the the debugging d

4、ebugging and and verification verification of of FPGA FPGA experimental experimental system. system. In In addition addition also also added added that that week, week, making making digital digital clock clock des

5、ign design features features more more perfect. perfect.Keywords: Keywords: QuartusII QuartusII EDA EDA FPGA FPGA 74LS192 74LS192 digital digital clock clock的 50Mhz 的頻率分成電路所需要的頻率來使用；計時電路將與靜、動態(tài)顯示電路相連，將時間與星期顯示在七段數(shù)碼管上，

6、保持電路作用時，系統(tǒng)停止計時并保持時間不變。其原理框圖如圖所示：三、 三、各模塊設(shè)計的說明 各模塊設(shè)計的說明1．分頻模塊 ．分頻模塊我實現(xiàn)分頻的方法是采用多個 74ls192 對 50MHz 的平率進行計數(shù)，由于 74ls192 每計十個脈沖從進位輸出一個脈沖，下一個 74ls192計上一個 74ls192 進位端輸出一的個脈開始計，相當(dāng)于下一個 74ls192計了 100 個脈沖才輸出一個脈沖，下一個計 1000 次才輸出一個脈沖，考