h.264解碼芯片中反變換和幀內(nèi)預(yù)測模塊的電路設(shè)計(jì)

1、華中科技大學(xué)碩士學(xué)位論文H.264解碼芯片中反變換和幀內(nèi)預(yù)測模塊的電路設(shè)計(jì)姓名：盧黎申請學(xué)位級別：碩士專業(yè)：軟件工程指導(dǎo)教師：鄒雪城20090525華 中 科 技 大 學(xué) 碩 士 學(xué) 位 論 文 華 中 科 技 大 學(xué) 碩 士 學(xué) 位 論 文 Abstract The technology of digital video find more and more comprehensive application because it i

2、s expressive, exact, effective and extensive. But we must improve the compression on the base of guaranteeing the quality of the video to make sure the effective application. H.264 is more excellence than the standard be

3、fore. It reduces the rate of bits half in the same quality of the video. The outstand level of performance is traded by the complexity of the algorithm. The task of this paper is to research the algorithm of the modules

4、of intraframe prediction and inverse transform which including IDCT(Inverse Discrete Cosine Transform) and IQ(Inverse Quantization) aimed at the video format of HDTV. This paper gives the instructions of the designs of t

5、he circuits which can implement these modules and the result of simulation. For the intraframe prediction decoder, this paper gives the exact instruction of the method to restore the reconstructed samples which can compr

6、omise between adopting the reference samples and restoring the reconstructed samples and make the interpolation easy. For the part of calculate the predicted samples, this paper gives a method which calculates the predic

7、ted samples in the same macroblock dividually and inserts the pipelines to eliminate multiplication and reduce the delay of the crucial path. The modules of intraframe prediction decode and the inverse transform is paral

8、lel to reduce the numbers of the decoding cycles and increase the throughput. This design is validating on the FPGA of Xilinx Virtex 2 Pro VP30. The throughput is 110.2Msamples/sec. The throughput to implement the decod