7.4ghz射頻接收機(jī)前端模塊的設(shè)計(jì)與實(shí)現(xiàn)

1、北京理工大學(xué)碩士學(xué)位論文7.4GHZ射頻接收機(jī)前端模塊的設(shè)計(jì)與實(shí)現(xiàn)姓名：陳鋮穎申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：@指導(dǎo)教師：仲順安;趙顯利@北京理工大學(xué)碩士學(xué)位論文 Abstract Nowadays, the application of wireless communication is becoming more and more wide. As the most important part of communication syst

2、em，the RF receiver is facing the challenge of high frequency， high integrity， low voltage， low power and low price. In order to improve the integrity of RF receiver，it is significant to improve the integrity of RF rece

3、iver analog module. Presently，the structure of RF receiver includes heterodyne receiver ， quasi-IF receiver, zero-IF receiver and wide width receiver. And digital IF-receiver is also used in design. This paper analyzes t

4、he integrity and improvement of zero-IF receiver，discusses the design of circuit，problems in design and solution. Based on that，I design the RF receiver module of low noise amplifier(LNA)，Mixer and voltage-controlled osc

5、illator (VCO) with 0.18um CMOS model and Cadence ADE. And the design meets the requirement of practical application and is the base for the further research. Key words: wireless receiver; RF CMOS element; low noise ampl