外文文獻(xiàn)翻譯----微控制器

1、<p><b>　　P89LPC952</b></p><p><b>　　1. 概述</b></p><p>　　P89LPC952 是一款單片封裝的微控制器，含有多種低成本的封裝形式。它采用了高性能的處理器結(jié)構(gòu)，指令執(zhí)行時間只需2 到4 個時鐘周期。6 倍于標(biāo)準(zhǔn)80C51 器件。P89LPC952集成了許多系統(tǒng)級的功能，這樣可大大減

2、少元件的數(shù)目和電路板面積并降低系統(tǒng)的成本。</p><p><b>　　2. 特性</b></p><p><b>　　2.1 主要特性</b></p><p>　　􀂄 8KB 可擦除Flash 程序存儲器，具有1KB 扇區(qū)和64 字節(jié)頁。單字節(jié)擦除特性使得任何字節(jié)都可用于非易失性數(shù)據(jù)存儲。</p&

3、gt;<p>　　􀂄 256 字節(jié) RAM 數(shù)據(jù)存儲器和256 字節(jié)附加片內(nèi)RAM。</p><p>　　􀂄 具有window 比較器的8 輸入多路10 位A/D 轉(zhuǎn)換器，結(jié)果在允許范圍以內(nèi)或以外</p><p>　　都可產(chǎn)生中斷。2 個模擬比較器可選擇輸入和參考源。</p><p>　　􀂄 2 個

4、16 位定時/計(jì)數(shù)器（每一個定時器均可設(shè)置為溢出時觸發(fā)相應(yīng)端口輸出或作為PWM 輸出），23 位的系統(tǒng)定時器可用作實(shí)時時鐘（RTC）。</p><p>　　􀂄 兩個增強(qiáng)型UART，具有波特率發(fā)生器、間隔檢測、幀錯誤檢測和自動地址檢測功能。400kHz 字節(jié)寬度的I2C 通信端口和SPI 通信端口。</p><p>　　􀂄 片內(nèi)高精度的RC 振蕩器選項(xiàng)帶有

5、時鐘倍頻器，無需外接振蕩器件?？蛇x擇RC 振蕩器選項(xiàng)并且其頻率可進(jìn)行很好的調(diào)節(jié)。內(nèi)部RC 振蕩器和任何振蕩器源之間的快速切換，提供低功耗有效模式的最佳支持，可快速轉(zhuǎn)變?yōu)樽罡咝阅堋?lt;/p><p>　　􀂄 VDD 操作電壓范圍為2.4～3.6V。I/O 口可承受5V（可上拉或驅(qū)動到5.5V）。</p><p>　　􀂄 44 腳封裝，使用片內(nèi)振蕩器和復(fù)位選項(xiàng)

6、時，至少可獲得40 個I/O 口。</p><p>　　􀂄 P5 的所有管腳可吸收/消耗高電流（20mA）。其它所有的端口管腳都有高消耗電流的能力（20mA）。整個芯片指定了最大值的限制。</p><p>　　􀂄 看門狗定時器具有獨(dú)立的片內(nèi)振蕩器，無需外接元件?？撮T狗預(yù)分頻器可從8 個值中選擇。</p><p><b>

7、　　2.2 其它特性</b></p><p>　　􀂄 當(dāng)操作頻率為18MHz 時，除乘法和除法指令外，高速80C51 CPU 的指令執(zhí)行時間為111~222ns。同一時鐘頻率下，其速度為標(biāo)準(zhǔn)80C51 器件的6 倍。只需要較低的時鐘頻率即可達(dá)到同樣的性能，這樣無疑降低了功耗和EMI。</p><p>　　􀂄 串行Flash 在電路編程（ICP

8、）可通過商用EPROM 編程器實(shí)現(xiàn)簡單的編程。Flash保密位可防止程序被讀出。</p><p>　　􀂄 串行Flash 在系統(tǒng)編程（ISP）可實(shí)現(xiàn)已固定在最終應(yīng)用上的器件的編程。</p><p>　　􀂄 Flash 程序存儲器可實(shí)現(xiàn)在應(yīng)用中編程（IAP）。這允許在程序運(yùn)行時改變代碼。</p><p>　　􀂄 低

9、電壓（掉電）檢測可在電源故障時使系統(tǒng)安全關(guān)閉。該功能也可配置為一個中斷。</p><p>　　􀂄 空閑和兩種不同的掉電節(jié)電模式。提供從掉電模式中喚醒功能（低電平中斷輸入喚</p><p>　　醒）。典型的掉電電流為1μA（比較器關(guān)閉時的完全掉電狀態(tài)）。</p><p>　　􀂄 低電平復(fù)位輸入可由任何內(nèi)部復(fù)位驅(qū)動。使用片內(nèi)上電復(fù)位時

10、不需要外接元件。復(fù)位計(jì)數(shù)器和復(fù)位干擾抑制電路可防止虛假和不完全的復(fù)位。另外還提供軟件復(fù)位功能。</p><p>　　􀂄 當(dāng)選擇片內(nèi)復(fù)位時，P89LPC952 只需連接電源和地。</p><p>　　􀂄 可配置的片內(nèi)振蕩器，其頻率可通過用戶可編程Flash 配置位進(jìn)行選擇。RC 振蕩器選項(xiàng)支持的頻率范圍為20kHz～18MHz。</p>&l

11、t;p>　　􀂄 振蕩器失效檢測?？撮T狗定時器具有獨(dú)立的片內(nèi)振蕩器，因此它可用于振蕩器的失效檢測。</p><p>　　􀂄 可編程I/O 口輸出模式：準(zhǔn)雙向口，開漏輸出，推挽和僅為輸入功能。</p><p>　　􀂄 端口“輸入模式匹配”檢測。當(dāng)P0 口管腳的值與一個可編程的模式匹配或者不匹配時，可產(chǎn)生一個中斷。</p>

12、<p>　　􀂄 可控制口線輸出斜率以降低EMI，輸出最小跳變時間約為10ns。</p><p>　　􀂄 4 個中斷優(yōu)先級。</p><p>　　􀂄 8 個鍵盤中斷輸入，另加2 路外部中斷輸入。</p><p>　　􀂄 施密特觸發(fā)端口輸入。</p><p>　　

13、􀂄 雙數(shù)據(jù)指針（DPTR）。</p><p>　　􀂄 擴(kuò)展的溫度范圍。</p><p><b>　　􀂄 仿真支持。</b></p><p>　　P89LPC952 Flash 存儲器</p><p><b>　　1.概述</b></p>

14、;<p>　　P89LPC952 Flash 存儲器提供電路中的電擦除和編程。Flash 可以字節(jié)為單位擦除、讀取或?qū)懭搿Ｉ葏^(qū)和頁擦除功能可擦除任意的Flash 扇區(qū)(1kB)或頁(64 字節(jié))。芯片擦除功能可實(shí)現(xiàn)整個程序存儲器的擦除。ICP 功能通過標(biāo)準(zhǔn)商用編程器來實(shí)現(xiàn)。另外，IAP 和字節(jié)擦除功能允許程序存儲器用作非易失性數(shù)據(jù)存儲器。片內(nèi)產(chǎn)生的擦除和寫入時序?yàn)橛脩籼峁┝擞押玫木幊探涌?。P89LPC952 Flash 存

15、儲器甚至在經(jīng)過100, 000 次擦除和編程周期后仍然能可靠地保存存儲器的內(nèi)容。存儲單元的設(shè)計(jì)優(yōu)化了擦除和編程機(jī)制。P89LPC952 使用VDD 電壓來執(zhí)行編程和擦除算法。</p><p><b>　　2.特性</b></p><p>　　?可在整個操作電壓范圍內(nèi)執(zhí)行編程和擦除。</p><p>　　?字節(jié)擦除允許程序存儲器用于存儲數(shù)據(jù)。&l

16、t;/p><p>　　?使用ISP/IAP/ICP 進(jìn)行讀/編程/擦除。</p><p>　　?內(nèi)部固化的引導(dǎo)ROM，包含了可用于用戶程序的低級IAP 子程序。</p><p>　　?默認(rèn)的裝載程序可通過串口進(jìn)行ISP 編程。該程序位于用戶程序存儲器空間的頂端。</p><p>　　?Boot 向量允許用戶將Flash 裝載代碼放入Flash 存

17、儲器內(nèi)的任何位置。這種配置為用戶提供了應(yīng)用的靈活性。</p><p>　　?任意Flash 編程/擦除時間小于2ms。</p><p>　　?使用工業(yè)標(biāo)準(zhǔn)的商用編程器進(jìn)行編程。</p><p>　　?可對每一個Flash 扇區(qū)進(jìn)行編程加密。</p><p>　　?每個字節(jié)至少可執(zhí)行100,000 次擦除/編程。</p><

18、p>　　?數(shù)據(jù)至少可保存10 年。</p><p>　　3.Flash 的結(jié)構(gòu)</p><p>　　P89LPC952 器件包含8 個1KB 扇區(qū)的Flash 程序存儲器。每個扇區(qū)可進(jìn)一步分成64 字節(jié)的頁。除了扇區(qū)擦除、頁擦除和字節(jié)擦除外，還包含一個64 字節(jié)的頁寄存器，它可實(shí)現(xiàn)給定頁1 到64 字節(jié)的同時編程，這徹底降低了整個編程的時間。</p><p>

19、　　4. Flash 用作數(shù)據(jù)存儲器</p><p>　　P89LPC952 的Flash 程序存儲器支持單個字節(jié)的擦除和編程。程序存儲器的任何一個字節(jié)都可通過MOVC 指令來讀取，只要包含該字節(jié)的扇區(qū)未加密（MOVC 指令不能讀取加密扇區(qū)的程序存儲器的內(nèi)容）。因此，非加密扇區(qū)的任何字節(jié)都可用來存儲非易失性數(shù)據(jù)。</p><p>　　5. Flash 的編程和擦除</p>&

20、lt;p>　　有4 種方法可實(shí)現(xiàn)對Flash 的編程或擦除。第一，在應(yīng)用固件的控制下，在最終用戶應(yīng)用程序中（IAP）對Flash 進(jìn)行編程或擦除。第二，使用ICP 功能。通過系統(tǒng)提供的串行時鐘/串行數(shù)據(jù)接口來實(shí)現(xiàn)ICP 編程。第三，出廠時，器件的用戶代碼空間的高512 字節(jié)包含一個串行ISP 程序，調(diào)用該程序通過串口來實(shí)現(xiàn)在電路編程。第四，使用支持該器件的商用EPROM 編程器進(jìn)行并行編程或擦除。該器件不提供對代碼內(nèi)容的直接校驗(yàn)。

21、而是提供一個扇區(qū)或整個用戶代碼區(qū)的32 位CRC 結(jié)果</p><p><b>　　附外文原文：</b></p><p><b>　　P89LPC952</b></p><p>　　1. General description</p><p>　　The P89LPC952 is a single-

22、chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks,six times the rate of standard 80C51 devices. Many system-level fu

23、nctions have been incorporated into the P89LPC952 in order to reduce component count, board space, and</p><p>　　system cost.</p><p>　　2. Features</p><p>　　2.1 Principal features<

24、/p><p>　　-- 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.Single-byte erasing allows any byte(s) to be used as non-volatile data storage.</p><p>　　--256-byte RA

25、M data memory and a 256-byte auxiliary on-chip RAM.</p><p>　　-- 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt for in or out of range results. Two analog comparators wit

26、h selectable inputs and reference source.</p><p>　　--Two 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output) and a 23-bit system timer that ca

27、n also be used as a RTC.</p><p>　　-- Two enhanced UARTs with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication

28、port and SPI communication port.</p><p>　　-- High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selec

29、table and fine tunable. Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance.</p><p>　　

30、-- 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).</p><p>　　--44-pin packages with 40 I/O pins minimum while using on-chip oscillator and reset options.&l

31、t;/p><p>　　-- Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip.</p><p&g

32、t;　　-- Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values.</p><p>　　2.2 Additional features</p><p>　　-- A h

33、igh performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at

34、the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.</p><p>　　--Serial flash In-Circuit Programming (ICP) allows simple production coding with

35、commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.</p><p>　　-- Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end

36、application.</p><p>　　-- In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application.</p><p>　　-- Low voltage (brownout) detect allows a gra

37、ceful system shutdown when power fails. May optionally be configured as an interrupt.</p><p>　　-- Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt

38、 input starts execution). Typical power-down current is 1 mA (total power-down with voltage comparators disabled).</p><p>　　-- Active-LOW reset input can be driven by any internal reset. On-chip power-on res

39、et allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.</p><p>　　--O

40、nly power and ground connections are required to operate the P89LPC952 when internal reset option is selected.</p><p>　　-- Configurable on-chip oscillator with frequency range options selected by user progra

41、mmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz.</p><p>　　-- Oscillator fail detect. The watchdog timer has a separate fully on-

42、chip oscillator allowing it to perform an oscillator fail detect function.</p><p>　　-- Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only.</p><p

43、>　　-- Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.</p><p>　　--Controlled slew rate port outputs to reduce EM

44、I. Outputs have approximately 10 ns minimum ramp times.</p><p>　　-- Four interrupt priority levels.</p><p>　　-- Eight keypad interrupt inputs, plus two additional external interrupt inputs.</

45、p><p>　　-- Schmitt trigger port inputs.</p><p>　　--Second data pointer.</p><p>　　--Extended temperature range.</p><p><b>　　附外文原文：</b></p><p>　　The

46、 P89LPC952 flash memory General description</p><p>　　--The P89LPC952 flash memory provides in-circuit electrical erasure and programming.</p><p>　　--The flash can be erased, read, and written as

47、 bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In

48、addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.</p><p>　　On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC952

49、 flash reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC952 uses VDD as the supply voltage to perform the Progr

50、am/Erase algorithms.</p><p><b>　　Features</b></p><p>　　? Programming and erase over the full operating voltage range.</p><p>　　? Byte erase allows code memory to be used

51、 for data storage.</p><p>　　? Read/Programming/Erase using ISP/IAP/ICP.</p><p>　　? Internal fixed boot ROM, containing low-level IAP routines available to user code.</p><p>　　? Defa

52、ult loader providing ISP via the serial port, located in upper end of user program memory.</p><p>　　? Boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providin

53、g flexibility to the user.</p><p>　　? Any flash program/erase operation in 2 ms.</p><p>　　? Programming with industry-standard commercial programmers.</p><p>　　? Programmable securi

54、ty for the code in the flash for each sector.</p><p>　　? 100,000 typical erase/program cycles for each byte.</p><p>　　? 10 year minimum data retention.</p><p>　　Flash organization&l

55、t;/p><p>　　--The program memory consists of eight 1 kB sectors on the P89LPC952 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase,and byte erase, a 64-byte

56、page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.</p><p>　　Using flash as data storage</p>&

57、lt;p>　　--The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the b

58、yte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.</p><p>　　Flash

59、programming and erasing</p><p>　　--Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the ap

60、plication’s firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space