微控制器外文翻譯

1、<p><b>　　原文：</b></p><p>　　Microcontroller-AT89S52</p><p>　　Features </p><p>　　Compatible with MCS -51Products</p><p>　　8K Bytes of In-System Programma

2、ble (ISP) Flash Memory</p><p>　　– Endurance: 10,000 Write/Erase Cycles</p><p>　　4.0V to 5.5V Operating Range</p><p>　　Fully Static Operation: 0 Hz to 33 MHz</p><p>　　Th

3、ree-level Program Memory Lock</p><p>　　256 x 8-bit Internal RAM</p><p>　　32 Programmable I/O Lines</p><p>　　Three 16-bit Timer/Counters</p><p>　　Eight Interrupt Sources

4、</p><p>　　Full Duplex UART Serial Channel</p><p>　　Low-power Idle and Power-down Modes</p><p>　　Interrupt Recovery from Power-down Mode</p><p>　　Watchdog Timer</p>

5、;<p>　　Dual Data Pointer</p><p>　　Power-off Flag</p><p>　　Fast Programming Time</p><p>　　Flexible ISP Programming (Byte and Page Mode)</p><p>　　Green (Pb/Halide-

6、free) Packaging Option1. Description</p><p>　　Description</p><p>　　The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. T

7、he device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogr

8、ammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic </p><p>　　The AT89S52 provides the following standard

9、features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, a

10、nd clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The 8Idle Mode stops the CPU while allowing the RAM

11、, timer/counters</p><p>　　Pin Description</p><p>　　VCC：Supply voltage.</p><p>　　GND：Ground.</p><p><b>　　Port 0</b></p><p>　　Port 0 is an 8-bit

12、open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multipl

13、exed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during p

14、rogram verification. External pull-ups ar</p><p><b>　　Port 1</b></p><p>　　Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source

15、four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I ) because

16、of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/</p><p><b>　　Port 2</b>

17、</p><p>　　Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-na

18、l pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I ) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from ext

19、ernal program memory and dur-ing accesses to external data memory that use 16-bit a</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.

20、The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pu

21、lled low will source current (I ) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S52, as</p

22、><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after

23、 the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.</p><p><b>　　ALE/PROG<

24、;/b></p><p>　　Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash progra

25、mming. </p><p>　　In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped

26、during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is we

27、akly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in e</p><p><b>　　PSEN</b></p><p>　　Program Store Enable (PSEN) is the read strobe to external pr

28、ogram memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. </p&g

29、t;<p><b>　　EA/VPP</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to

30、 FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V for internal program executions.This pin also receives the 12-volt programming enable voltage (V

31、 ) during Flash programming.</p><p>　　XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　XTAL2：Output from the inverting oscillator amp

32、lifier.</p><p>　　Timer 0 and Timer1</p><p>　　Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the </p><p>　　AT89C51 and AT89C52. For further informa

33、tion on the timers’ operation, please click on the </p><p>　　document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

34、 </p><p><b>　　Timer 2</b></p><p>　　Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the

35、 SFR T2CON (shown in Table 5-2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 10-1. Timer 2 consists o

36、f two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle cons</p><p>　　5. Interrupts</p><p>　　The AT89S52 has a total

37、 of six interrupt vectors: two external interrupts (INT0 and INT1), three </p><p>　　timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually e

38、nabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.IE.6 is unimplemented. User software should not write a 1

39、to this bit position, since it may be used in future AT89 products.Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. N</p><p>　　Reference data:</p><p>　　1.

40、 the ATMEL company AT89S52 technical manuals</p><p>　　2.Shenzhen Development Co., Ltd. AT89C52 Datasheets source SCM</p><p>　　3.Fudan University Press, single-chip microprocessor theory, applica

41、tion and test ZHANG You-de, etc</p><p><b>　　譯文：</b></p><p>　　微控制器-AT89S52</p><p><b>　　主要性能</b></p><p>　　與MCS-51單片機產(chǎn)品兼容</p><p>　　8K字

42、節(jié)在系統(tǒng)可編程Flash存儲器</p><p><b>　　1000次擦寫周期</b></p><p>　　4.0V至5.5V的工作電壓</p><p>　　全靜態(tài)操作：0Hz～33Hz</p><p><b>　　三級加密程序存儲器</b></p><p>　　256 &#

43、215; 8位內(nèi)部RAM的</p><p>　　32個可編程I/O口線</p><p>　　三個16位定時器/計數(shù)器</p><p><b>　　八個中斷源</b></p><p>　　全雙工UART串行通道</p><p>　　低功耗空閑和掉電模式</p><p><

44、;b>　　掉電后中斷可喚醒</b></p><p><b>　　看門狗定時器</b></p><p><b>　　雙數(shù)據(jù)指針</b></p><p><b>　　掉電標識符</b></p><p><b>　　快速編程時間</b><

45、/p><p>　　靈活的ISP編程（字節(jié)和頁模式）</p><p><b>　　1. 功能特性</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K 在系統(tǒng)可編程Flash 存儲器。使用Atmel公司高密度非易失性存儲器技術制造，與工業(yè)80C51產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程

46、，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8 位CPU 和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應用系統(tǒng)提供高靈度、超有效的解決方案。</p><p>　　AT89S52具有以下標準功能：8k字節(jié)Flash，256字節(jié)RAM，32位I/O口線，看門狗定時器，2個數(shù)據(jù)指針，三16位片內(nèi)晶振及時鐘電路。另外，AT89S52可降至0Hz靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止

47、工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結，單片機一切工作停止，直到下一個中斷或硬件復位為止。</p><p><b>　　引腳描述</b></p><p><b>　　VCC : 電源</b></p><p><b>　　GND: 地</b>

48、</p><p><b>　　P0 口</b></p><p>　　P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅動8個TTL邏</p><p>　　輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。</p><p>　　當訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復用。在這種模式下，P0具

49、有內(nèi)部上拉電阻。在flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。</p><p><b>　　P1 口</b></p><p>　　P1 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p1 輸出緩沖器能驅動4 個TTL 邏輯電平。對P1 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使

50、用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX）</p><p><b>　　P2 口</b></p><p>　　P2 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2 輸出緩沖器能驅動4 個TTL 邏輯電平。對P2 端口

51、寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2 口送出高八位地址。在這種應用中，P2 口使用很強的內(nèi)部上拉發(fā)1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內(nèi)容。</p><p>　　在flash編程

52、和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。</p><p><b>　　P3 口</b></p><p>　　P3 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p2 輸出緩沖器能驅動4 個TTL 邏輯電平。對P3 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出流（IIL）。<

53、;/p><p>　　P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗時，P3口也接收一些控制信號。</p><p><b>　　RST</b></p><p>　　復位輸入。晶振工作時，RST腳持續(xù)2 個機器周期高電平將使單片機復位。看門狗計時完成后，RST 腳輸出96個晶振周期的高電平。特殊寄存器AUXR(地

54、址8EH)上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復位高電平有效。</p><p><b>　　ALE/PROG</b></p><p>　　地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低8 位地址的輸出脈沖。在flash編程時，此引腳（PROG）也用作編程輸入脈沖。</p><p>　　在一般情況下，ALE 以晶

55、振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。如果需要，通過將地址為8EH的SFR的第0位置“1”，ALE操作將無效。這一位置 “1”，ALE僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE將被微弱拉高。這個ALE 使能標志位（地址為8EH的SFR的第0位）的設置對微控制器處于外部執(zhí)行模式下無效。</p><p><b>

56、;　　PSEN</b></p><p>　　外部程序存儲器選通信號（PSEN）是外部程序存儲器選通信號。</p><p>　　當AT89S52從外部程序存儲器執(zhí)行外部代碼時，PSEN在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，PSEN將不被激活。</p><p><b>　　EA/VPP</b></p><

57、;p>　　訪問外部程序存儲器控制信號。為使能從0000H到FFFFH的外部程序存儲器讀取指令，EA必須接GND。為了執(zhí)行內(nèi)部程序指令，EA應該接VCC。</p><p>　　在flash編程期間，EA也接收12伏VPP電壓。</p><p>　　XTAL1：振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端。

58、</p><p>　　3.定時器0和定時器1</p><p>　　在AT89S52中，定時器0和定時器1的操作與AT89C51和AT89C52一樣。為了獲得更深入的關于UART的信息，可參考ATMEL網(wǎng)站（http://www.atmel.com）。</p><p><b>　　4. 定時器2</b></p><p>　

59、　定時器2是一個16位定時/計數(shù)器，它既可以做定時器，又可以做事件計數(shù)器。其工作方式由特殊寄存器T2CON中的C/T2位選擇（如表2所示）。定時器2有三種工作模式：捕捉方式、自動重載（向下或向上計數(shù)）和波特率發(fā)生器。如表3 所示，工作模式由T2CON中的相關位選擇。定時器2 有2 個8位寄存器：TH2和TL2。在定時工作方式中，每個機器周期，TL2 寄存器都會加1。由于一個機器周期由12 個晶振周期構成，因此，計數(shù)頻率就是晶振頻率的1/

60、12。</p><p><b>　　中斷</b></p><p>　　AT89S52有6個中斷源：兩個外部中斷（INT0和INT1），三個定時中斷（定時器0、1、2）和一個串行中斷。每個中斷源都可以通過置位或清除特殊寄存器IE 中的相關中斷允許控制位分別使得中斷源有效或無效。IE還包括一個中斷允許總控制位EA，它能一次禁止所有中斷。IE.6位是不可用的。對于AT89S

61、52，IE.5位也是不能用的。用戶軟件不應給這些位寫1。它們?yōu)锳T89系列新產(chǎn)品預留。定時器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進入中斷服務后，這些標志位都可以由硬件清0。實際上，中斷服務程序必須判定是否是TF2 或EXF2激活中斷，標志位也必須由軟件清0。定時器0和定時器1標志位TF0和TF1在計數(shù)溢出的那個周期的S5P2被置位。它們的值一直到下一個周期被電路捕捉下來。然而，定時器2 的標志位TF2 在計數(shù)溢

62、出的那個周期的S2P2被置位，在同一個周期被電路捕捉下來。</p><p><b>　　參考資料：</b></p><p>　　1．ATMEL公司AT89S52的技術手冊</p><p>　　2．深圳市中源單片機發(fā)展有限公司AT89C52 Datasheets</p><p>　　3．復旦大學出版社單片微型機原理、應用和