通信線路的多模式管理外文翻譯

1、<p>　　附錄二 英文文獻(xiàn)及譯文</p><p>　　MULTI-MODE MANAGEMENT OF A SERIAL COMMUNICATION LINK </p><p>　　BACKGROUND</p><p>　　A. Technical Field</p><p>　　The present invention r

2、elates generally to signal processing, and more particularly, to the management of a serial communication link between two components, such as a serializer/deserializer ("SERDES") and a transceiver. </p>

3、<p>　　B. Background of the Invention</p><p>　　In a communication device, data can be transmitted from one component to another component by a serial or parallel data transfer. With the rapid improvemen

4、t in networking technologies, there is a great demand for high speed component- 15 to-component communication rates in order to move larger amounts of data more efficiently within a networking device.</p><p>

5、;　　High-speed serial links are being interfaced between networking components to achieve these communication rate increases. The actual data rates on these links may be defined by various protocols and standards, such as

6、 the System Packet Interface Level 4 (SPI-4) protocol that covers a spectrum of 622 Mb/s to rates above 1 Gb/s.</p><p>　　A SERDES may interface a parallel data bus with a serial link by effectively serializi

7、ng or deserializing a data signal. SERDES technology has become very important as data rates have continually increased because a very fast serial link may be converted to a deserialized signal that can be more easily tr

8、ansmitted and processed on a parallel data bus.</p><p>　　FIG. 1 illustrates an exemplary SERDES and interfacing component(s) according to one embodiment of the invention. In this particular example, a SERDES

9、 101 interfaces either a 64 or 128 bit parallel bus 103 to a serial data link 105. The serial data link 105 is also coupled to a transceiver 102. In the operation of a system, the rate of the system core logic may operat

10、e at a different rate than the serial data link 105 because of the parallel transfer of data to the core logic.</p><p>　　In one example, the SERDES 101 serial interface receives an 8-bit data stream clocked

11、at 500 MHz and forwards the data to the core logic in a 16-bit data stream clocked at 250 MHz. The clock difference between the SERDES 101 interface and the system core logic may be synthesized and mapped to a structure

12、such as an ASIC or FPGA located within the data path to compensate for this clock mismatch. However, if the same serial interface on the SERDES 101 receives an 8-bit data stream clocked at 1 GH</p><p>　　Cur

13、rent ASIC and FPGA technology is unable to cost effectively provide an ASIC or FPGA that achieves the required clocking speed of 500 MHz or above for core logic processing. In order to increase the required data rate at

14、 the system core logic, the width of the parallel data bus may be expanded by a factor of two. Consequently, in this particular example, the parallel data bus may be expanded to 64-bit or wider to reduce the required int

15、ernal core logic clocking speed.</p><p>　　The principle of expanding parallel data bus width may be extrapolated to achieve higher data rates without having to increase a corresponding clocking speed. For ex

16、ample, the 64-bit parallel bus could be changed to a 128-bit or 256-bit to reduce the clock frequency of 500 MHz to half or one-fourth respectively.</p><p>　　One current solution in which variable width data

17、 buses are provided is by generating multiple system design versions in which different inputs and clock frequencies are associated with each clocking speed and input. However, creating multiple version of a system desi

18、gn may become logistically difficult because of the creation and maintenance of multiple source codes related to the design. Further, the verification environment and process may become overly complicated which may requi

19、re support </p><p>　　Therefore there is a need for providing a single system design that allows multiple parallel data widths and clock inputs in order to facilitate the speed matching of a component, such a

20、s core logic, to the serial interface of a SERDES or other component.</p><p>　　SUMMARY OF THE INVENTION</p><p>　　A system, apparatus and method that provide data management between a serial inte

21、rface and other component are described. In one embodiment, the present invention may manage a data stream between a SERDES and a transceiver. A variable length serial data stream is received at a buffer manager located

22、between the SERDES and transceiver. The data within the buffer manager is controlled by a state machine that is advanced by event scheduler logic. The event scheduler logic provides different modes i</p><p>

23、　　In one embodiment of the invention, a 64-bit data stream or 128-bit data stream may be communicated on a serial link between a SERDES and transceiver. A buffer manager is serially coupled within the serial link to allo

24、w the serial transmission of data in two different modes corresponding to the two different bus widths at the parallel interface of the SERDES. A state machine interfaces with the buffer manager and event scheduler logic

25、 to facilitate the different data streams. The state machine p</p><p>　　The event scheduler may operate in a plurality of different modes depending on the rate at which data needs to be communicated on the s

26、erial link. In one mode, the state machine may progresses data on the serial link at every cycle of a core clock rate provided by the event scheduler logic and an internal clock. In a second mode, the state machine may p

27、rogresses data on the serial link at every other cycle of the core clock rate; thereby effectively reducing the effective data rate on the serial</p><p>　　Other objects, features and advantages of the invent

28、ion will be apparent from the drawings, and from the detailed description that follows below.</p><p>　　BRIEF DESCRIPTION OF THE DRAWINGS</p><p>　　Reference will be made to embodiments of the inv

29、ention, examples of which may be illustrated in the accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in the context of these embodiments, it

30、 should be understood that it is not intended to limit the scope of the invention to these particular embodiments.</p><p>　　FIG. 1 illustrates a prior art system where a serial interface on a SERDES is commu

31、nicating a serial data stream at a particular data rate.</p><p>　　FIG. 2 illustrates a variable data rate serial communication link operating in a first mode between a SERDES and another component according

32、to one embodiment of the invention.</p><p>　　FIG. 3 illustrates a variable data rate serial communication link operating in a second mode between a SERDES and another component according to one embodiment of

33、 the invention.</p><p>　　FIG. 4 shows a diagram illustrating multi-mode operation 5 of a multi-mode buffer manager and state machine within a serial communication link according to one embodiment of the inve

34、ntion.</p><p>　　DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS</p><p>　　In the following description, for purpose of explanation, specific details are set forth in order to provide an underst

35、anding of the invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention,

36、 some of which are described below, may be incorporated into a number of different computing systems and devices. The embodiments of the present invention may b</p><p>　　Reference in the specification to &q

37、uot;one embodiment" or "an embodiment" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the inve

38、ntion. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment. </p><p>　　A. Overview</p><p>　

39、　A system, apparatus and a method for managing the communication of data between a serial interface on a SERDES and other component, such as a transceiver, are disclosed. This actual management of data may depend on the

40、bus width that is coupled to the parallel interface on the SERDES.</p><p>　　A buffer manager is serially coupled within a communication link between the SERDES and other component. The buffer manager is cou

41、pled to a state machine and event scheduler logic that operate in one of a plurality of modes associate with different parallel bus widths at the other side of the SERDES. In particular, the event scheduler controls the

42、rate at which the state machine progresses data on the serial link. In one embodiment, the state machine may operate at a core clocking rate, or fract</p><p>　　The variable rate of data progression on the se

43、rial link allows the link to interface, via a SERDES, with multiple buses having different widths and associated clocking rates. </p><p>　　B. Multi-Mode Buffer Manager and Event Scheduler Logic</p>&

44、lt;p>　　FIG. 2 illustrates a multi-mode buffer manager and event scheduler logic operating in a first mode. In this particular embodiment, the first mode 204 operates at a rate associated with a 64-bit parallel bus clo

45、cked at a particular rate. How ever, this first mode may operate within other parallel buses such as a 128-bit, 256-bit or 512-bit buses depending on the particular application of the serial communication link. Event sch

46、edule logic 203, a state machine 202 and a buffer manager 201 are show</p><p>　　The progression of data through the buffer manger 201 is controlled by the state machine 202, which in turn is enabled or disab

47、led by event scheduler logic 203. The event scheduler logic 203 advances events or data progressions of the state machine 202 according to a timing signal 240 provided to the event scheduler logic 203. This timing signal

48、 240 may be generated by processing an internal clock and in which the buffer manager 201 and state machine 202 are operating. For example, in one embodi</p><p>　　The multiplexer 230, within the event schedu

49、ler logic 203, receives a series of alternating bits from the flip-flop 220 at a particular core clock rate. A select line is coupled to the multiplexer 230 that controls its output. This multiplexer output is the timing

50、 signal 240 that controls the rate at which the state device 202 progresses data on the link. The number of select lines may be increased to increase the number of modes and effective data rates in which the state device

51、 202 may operate</p><p>　　Reset functionality may be included within the event scheduler 203 to allow a user to reset the system. In this particular embodiment, a reset pin located on the flip-flop 220 is sh

52、own.</p><p>　　通信線路的多模式管理</p><p><b>　　背景</b></p><p><b>　　1 技術(shù)領(lǐng)域</b></p><p>　　本專利通常涉及到信號處理,而更特別的是,兩個(gè)設(shè)備的串行通信的管理,例如并串行轉(zhuǎn)換器/ 串并行轉(zhuǎn)換器(“SERDES”)和一個(gè)收發(fā)器。&l

53、t;/p><p><b>　　2 專利的背景</b></p><p>　　在通信設(shè)備中，數(shù)據(jù)可以通過串行或并行方式從一個(gè)設(shè)備傳輸?shù)搅硪辉O(shè)備中。隨著網(wǎng)絡(luò)技術(shù)的迅速發(fā)展, 為了在一個(gè)網(wǎng)絡(luò)裝置中更有效地傳輸更大的數(shù)據(jù)流量,對于設(shè)備之間的通信速率有了更高的要求。</p><p>　　為了使通信速率提高，通信網(wǎng)路組件之間的高速串行線路正在聯(lián)結(jié)。在這些通信線路

54、中，實(shí)際的數(shù)據(jù)傳輸速率可能根據(jù)各種不同的協(xié)議和標(biāo)準(zhǔn)確定，如系統(tǒng)SPI-4界面四級(包)協(xié)議,包含了一個(gè)從622 Mb / s的比率到以上的范圍。</p><p>　　通過有效地將一串?dāng)?shù)據(jù)信號串行化或并行化，一個(gè)并行轉(zhuǎn)換器可以把一個(gè)并行線路連接到一個(gè)串行數(shù)據(jù)線路上。由于數(shù)據(jù)率的不斷增加,也因?yàn)橐粋€(gè)非常快的串行線路可以轉(zhuǎn)換成一串并行數(shù)據(jù)信號，這種信號在并行數(shù)據(jù)總線上更易于傳輸與處理，并行轉(zhuǎn)換技術(shù)已經(jīng)變得非常重要。&l

55、t;/p><p>　　圖1根據(jù)本專利的一種具體化，舉例說明了一個(gè)典型的并行轉(zhuǎn)換器和接口組件。在這個(gè)特定的例子中,一個(gè)并行轉(zhuǎn)換器101可以將一個(gè)64位或128位的并行總線103連接到一個(gè)串行數(shù)據(jù)線路105上。這個(gè)串行數(shù)據(jù)線路105也是耦合到一個(gè)收發(fā)器102上。在操作系統(tǒng)中,這一系統(tǒng)核心邏輯速率可以以一種不同的速率運(yùn)行，這個(gè)速率比串行數(shù)據(jù)線路105快，這是因?yàn)閿?shù)據(jù)并行轉(zhuǎn)換到核心邏輯。</p><p&g

56、t;　　在一個(gè)例子中,并行轉(zhuǎn)換器101串行接口以500MHZ的速率接收到一串8位數(shù)據(jù)流，并以250MHZ的速率發(fā)送16位數(shù)據(jù)流到核心邏輯上。SERDES 101數(shù)據(jù)接口與系統(tǒng)核心邏輯之間的系統(tǒng)時(shí)鐘差異可合成和映射到一個(gè)結(jié)構(gòu)上，例如通過ASIC或FPGA區(qū)域范圍內(nèi)的數(shù)據(jù)路徑來彌補(bǔ)這個(gè)時(shí)鐘不匹配。然而, 在SERDES 101上，如果同樣的串行接口以500MHZ的速率收到一串8位數(shù)據(jù)流,然后系統(tǒng)核心邏輯需要以500MHZ的速率才能較好地處理

57、一個(gè)相應(yīng)的16位數(shù)據(jù)流。</p><p>　　目前的ASIC和FPGA技術(shù)不能有效地提供ASIC或FPGA來實(shí)現(xiàn)要求的時(shí)鐘速率5００MHZ或以上來更好地進(jìn)行核心邏輯處理。為了提高在系統(tǒng)核心邏輯中的數(shù)據(jù)傳輸速率,并行數(shù)據(jù)總線的數(shù)據(jù)寬度可以被擴(kuò)展到兩倍。因此,在這個(gè)特定的例子,并行數(shù)據(jù)總線可以擴(kuò)展到64位或更寬來減少所需的內(nèi)部核心邏輯時(shí)鐘速度。</p><p>　　擴(kuò)大并行數(shù)據(jù)總線寬度的原則是

58、無需增加相應(yīng)時(shí)鐘速度的條件下，擴(kuò)大數(shù)據(jù)總線寬度可以達(dá)到更高的數(shù)據(jù)速率。例如, 64位并行數(shù)據(jù)總線可以擴(kuò)大為128位或256位，這樣就將500MHZ的時(shí)鐘頻率降低到它的八分之一。</p><p>　　解決可變寬度的數(shù)據(jù)總線的一個(gè)當(dāng)前的方案是產(chǎn)生多個(gè)系統(tǒng)的設(shè)計(jì)版本，將不同的輸入和時(shí)鐘頻率與各時(shí)鐘速度和輸入連接起來。但是,建立多個(gè)版本的系統(tǒng)設(shè)計(jì)可能帶來邏輯上的一些因難，因?yàn)檫@樣就會需要?jiǎng)?chuàng)造和維護(hù)與設(shè)計(jì)相關(guān)的多源編碼。另

59、外,測試環(huán)境和過程可能變得過于復(fù)雜,可能需要技術(shù)支持工程師為多個(gè)客戶使用的不同版本的系統(tǒng)設(shè)計(jì)更新補(bǔ)丁。</p><p>　　這樣, 為了方便通信設(shè)備的速度匹配，我們需要提供單一的系統(tǒng)設(shè)計(jì)來允許多個(gè)并行數(shù)據(jù)寬度和時(shí)鐘輸入,如核心邏輯,對于一個(gè)SERDES的串行接口或其他組件。</p><p>　　本專利對一個(gè)提供了串行接口與其他組件之間的數(shù)據(jù)管理的系統(tǒng)、儀器和方法進(jìn)行了描述。在一個(gè)實(shí)例中,本

60、專利可以管理SERDES和一個(gè)收發(fā)器之間的數(shù)據(jù)流。一種可變長度的串行數(shù)據(jù)流被發(fā)送到位于SERDES和收發(fā)器之間的緩沖器和收發(fā)器中。緩沖器中的數(shù)據(jù)的控制是通過一個(gè)狀態(tài)機(jī)，而狀態(tài)機(jī)是通過事件調(diào)度程序邏輯來推動的。這一事件調(diào)度程序邏輯提供了不同模式，在這些模式中，可變傳輸速率的數(shù)據(jù)流可能在SERDES和發(fā)射機(jī)之間通訊。</p><p>　　在本專利的一個(gè)具體例子中,一個(gè)64位的數(shù)據(jù)流或128位數(shù)據(jù)流可以在一個(gè)SERDE

61、S和收發(fā)器之間的一個(gè)串行鏈路通訊。一個(gè)緩沖器是連續(xù)的耦合在串行線路中的，并且在SERDES的并行接口上，允許串行傳輸?shù)臄?shù)據(jù)在兩種不同的模式下對應(yīng)于兩種不同總線寬度進(jìn)行數(shù)據(jù)傳輸。一個(gè)狀態(tài)機(jī)與緩沖管理器和事件調(diào)度邏輯連接起來來促進(jìn)不同的數(shù)據(jù)流的傳輸。在多種數(shù)據(jù)傳輸速率碼流中，狀態(tài)機(jī)傳輸數(shù)據(jù)是根據(jù)它的運(yùn)行模式來傳輸?shù)摹?lt;/p><p>　　根據(jù)串行線路中不同數(shù)據(jù)傳輸需要的的速率，這一事件調(diào)度器可在一組不同的模式下運(yùn)行。

62、在一個(gè)模式下，狀態(tài)機(jī)可以促進(jìn)數(shù)據(jù)在每個(gè)周期中由事件調(diào)度邏輯器和一內(nèi)置的時(shí)鐘所提供的一個(gè)核心時(shí)鐘頻率的串行線路中的傳輸。在另一個(gè)模式中，狀態(tài)機(jī)可能促進(jìn)數(shù)據(jù)在每隔一個(gè)周期的核心時(shí)鐘頻率下傳輸,從而顯著地成倍地提高了在串行線路中有效數(shù)據(jù)的傳輸速率。也可以重置邏輯并且耦合到事件調(diào)度器中，進(jìn)一步控制事件的調(diào)度。</p><p>　　其他關(guān)于本專利的主旨、特點(diǎn)和優(yōu)勢將通過從圖紙以及下面的詳細(xì)描述來闡明。</p>

63、<p><b>　　簡短的圖紙描述</b></p><p>　　下面將會提及本專利的具體方面。這些具體方面的例子會通過具體的數(shù)字來說明。這些數(shù)據(jù)旨在說明,而不是限制。一般來說，雖然在這些具體的例子中描述這個(gè)專利,但是應(yīng)該要了解的是,這并不意味著將專利限制在這些特定的例子中。</p><p>　　圖1舉例說明了一個(gè)優(yōu)先的技術(shù)系統(tǒng),在該系統(tǒng)中，SERDES上的

64、一個(gè)串行接口在一個(gè)特定的數(shù)據(jù)傳輸率下傳輸數(shù)據(jù)。</p><p>　　圖2中，根據(jù)本專利的一個(gè)具體例子，一個(gè)可變數(shù)據(jù)傳輸率的串行通信線路在SERDES和另一個(gè)組件之間的第一個(gè)模式中運(yùn)行。</p><p>　　圖3中，根據(jù)本專利的一個(gè)具體例子，一個(gè)可變數(shù)據(jù)傳輸率的串行通信線路在SERDES和另一個(gè)組件之間的第二個(gè)模式中運(yùn)行。</p><p>　　圖4中，根據(jù)本專利的一個(gè)

65、具體例子，圖表顯示了多模態(tài)緩沖器和狀態(tài)機(jī)在串行通信線路中的多模態(tài)的操作系統(tǒng)。</p><p><b>　　優(yōu)先權(quán)的詳細(xì)介紹</b></p><p>　　在接下來的描述中,為了更好的闡述和了解本專利,已經(jīng)做出了具體的細(xì)節(jié)描述。很顯然的,對于本領(lǐng)域的熟練技術(shù)人員來說，沒有這些細(xì)節(jié)同樣可以更好的進(jìn)行實(shí)踐。本領(lǐng)域中熟練的技術(shù)人員將意識到本專利的例子中，其中有一些在下面的描述中

66、,也許被納入了許多不同的計(jì)算系統(tǒng)和設(shè)備。本專利可存在于硬件或固件。在框圖中展現(xiàn)的結(jié)構(gòu)和設(shè)備是對本專利的典型例子,用來避免對本專利一些方面的不明白。此外,在數(shù)據(jù)中的各組件之間的連接不應(yīng)該只局限于直接連接。更確切的說,這些組件之間的數(shù)據(jù)可能需要通過中介部件來修改,重置或是其他方式的改變。</p><p>　　參考規(guī)范中“一中例子”或“這種例子”是指一個(gè)特定的特點(diǎn)、結(jié)構(gòu)、特點(diǎn)、功能或描述與此有關(guān)的例子,是包括至少一個(gè)例

67、子的專利。短語“在一個(gè)例子中”的出現(xiàn)，在說明書的很多地方中不一定是引用同一個(gè)例子。</p><p><b>　　1概述</b></p><p>　　在一個(gè)SERDES串行接口和其他組件之間,一個(gè)管理數(shù)據(jù)傳輸?shù)南到y(tǒng)、儀器和方法，例如一個(gè)公開的無線電收發(fā)機(jī)。這種實(shí)際的管理數(shù)據(jù)可以依靠總線寬度耦合到SERDES上的并行接口上。</p><p>　　一

68、個(gè)緩沖器連續(xù)的耦合在SERDES和其他組件之間的通信線路上。這個(gè)緩沖器耦合到一個(gè)狀態(tài)機(jī)和事件調(diào)度器中，他們在一組模式中的一種下運(yùn)行，這些模式與不同的并行數(shù)據(jù)寬度聯(lián)系在一起，且在SERDES的另一邊。值得一提的是,該事件調(diào)度器控制數(shù)據(jù)狀態(tài)機(jī)的串行線路的數(shù)據(jù)傳輸速率。在一個(gè)實(shí)例中,狀態(tài)機(jī)可以在核心時(shí)鐘計(jì)時(shí)率下運(yùn)行,或是稍微小的速率，這取決于它當(dāng)前正在運(yùn)行的模式。</p><p>　　在串行線路中的變量數(shù)據(jù)傳輸率允許通

69、過SERDES連接到一個(gè)接口上，因?yàn)槎嗦房偩€有不同寬度及與之相關(guān)的時(shí)鐘率。</p><p>　　2.多模緩沖器和事件調(diào)度程序邏輯器</p><p>　　圖2說明了多模態(tài)緩沖管理器和事件調(diào)度程序邏輯器的運(yùn)行在第一種模式下。在這個(gè)特定的例子中,第一種模式204運(yùn)行在一個(gè)與64位并行總線的特定傳輸速率相關(guān)速率下。但是,第一個(gè)模式可能工作在其他并行數(shù)據(jù)總線下,如128位，256位或512位，這取決

70、于特定應(yīng)用程序的串行通信線路。如下所示的事件程序邏輯器203,一個(gè)狀態(tài)機(jī)202和一個(gè)緩沖管理器201。</p><p>　　傳輸?shù)臄?shù)據(jù)通過緩沖管理器201是由狀態(tài)機(jī)202控制的,反過來狀態(tài)機(jī)202是由調(diào)度程序邏輯器203啟用或禁用的。這一事件調(diào)度程序邏輯器203傳輸狀態(tài)機(jī)的202的事件或數(shù)據(jù)是根據(jù)提供給事件調(diào)度程序邏輯器203的定時(shí)信號240來傳輸?shù)?。定時(shí)信號240可能是由通過處理一個(gè)內(nèi)部時(shí)鐘而產(chǎn)生的，并且它聯(lián)系

71、著一個(gè)特定的時(shí)鐘速度的模式，緩沖管理器201和狀態(tài)機(jī)202在此模式中運(yùn)行。例如,在本專利中的一個(gè)例子中,觸發(fā)器220和多路轉(zhuǎn)接器230組合起來創(chuàng)建定時(shí)信號240，此定時(shí)信號正比于內(nèi)部時(shí)鐘的核心的計(jì)時(shí)率。特別需要指出的是,多路轉(zhuǎn)換器230可以產(chǎn)生定時(shí)信號240或等于核心計(jì)時(shí)率或稍微慢于核心計(jì)時(shí)率，這取決于所選擇的一種操作方式。本領(lǐng)域熟練的技術(shù)人員將會認(rèn)識到,數(shù)據(jù)傳輸通過緩沖管理器,狀態(tài)機(jī)時(shí)的有效速率可能在大范圍的數(shù)據(jù)寬度和時(shí)鐘速度中有所變

72、動，而專利可以有效地產(chǎn)生和將這些數(shù)據(jù)寬度和時(shí)鐘速度編碼。</p><p>　　在調(diào)度程序邏輯器203中, 多路轉(zhuǎn)換器230接收到觸發(fā)器220在某一特定的核心的時(shí)鐘頻率下的一系列交替的二進(jìn)制碼。一個(gè)選擇線耦合到控制其輸出的多工器230。這個(gè)多工器的輸出是定時(shí)信號240,這個(gè)定時(shí)信號可控制在狀態(tài)機(jī)在數(shù)據(jù)線路上的傳輸速率。選擇線數(shù)量的增加可以增加狀態(tài)機(jī)202工作的模式的數(shù)量和有效的數(shù)據(jù)傳輸率。本領(lǐng)域熟練的技術(shù)人員將會認(rèn)