1.5伏，98db動(dòng)態(tài)范圍sigmadelta調(diào)制器研究與設(shè)計(jì)

1、電子科技大學(xué)碩士學(xué)位論文1.5伏，98dB動(dòng)態(tài)范圍sigmadelta調(diào)制器研究與設(shè)計(jì)姓名：鄭浩申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：微電子學(xué)與固體電子學(xué)指導(dǎo)教師：葉星寧20060201AbsⅡ丑ctAbstractInrecentyears，oversamplingtechniquesbasedonsigma—deltamodulationarewidelyusedtoimplenl饑ttlleintcrfacesbctwe饑趴alog肌dd酒ta

2、lsignalsinVLsIsystemsThiskindoftecIlIliquecaIlo仃ernumerousadVantagesfortherealizati_6nofhighresolutionanalo爭(zhēng)to—di百talconVeners(ADcs)，andbeinsensitiVetoprocessvariationsInomerways，ttlearchitectllreispowere伍cientmeansofimp

3、l∞1e塒ngADcsAdo砸ngsui協(xié)1e10w—v01tagetedlniquescanmakecir∞itsworkwellInthisthesis，Ⅱ1emeoryaIldpar鋤etersofADC，tllemeoryoffirst—ordcrandhi曲一ordersigmadeltamodulatorshavebeenintroduccdunfortllnately，memodulatorsofhigherorderar

4、einherennyunstable，sousingcascadedsigmadeltamodulatorsissuitableEspecia11y，themismatchoft11ecascadedmodulator踟dnon—idealcharactersofswitchedcapacitorintcgratorhavebeendiscussed11let11ree—ordermoduIatorhasa21cascadedstrIl

5、cture柚d1bitquantizerattlleendofeachstage，themodulatorisimplefnented耐m如11ydif!fh∞tialswitched—c印acitorcircuitsAndthcn，thediscussionwillbeginbyexploringthedesignofv砌ouscircuitblocksintllemodulatorinmoredetail，ie，OTA，switch

6、ed—c印acitorinteg陽(yáng)tor，quantizeLtwo—phasenon—oVe訂appingclocksignal，etc，atmesalTletime，thesecircujtswillbesimulatedinSpectrcaIldHspiceAtlast，thewholecascadedmodulatorwiUdobehaviorallevelsimulationbyMATLABsoftandSIMULINKTool

7、boxTheproposedmodulatorusesO35umstandardCMOSprocess，t11eNMOSaIldPMoSthresh01dv01tageisO54voltan“048volt，respectiVely，andt11epowersupplyis15volt111eNyquistconvertcrrateis50l【Hz，oVcrsamplingratiois80111eproposedmodulatorca

8、nobtain98dBdyn鋤icrange，l6bitsconvertcrresolution，andfitsforhi曲面del“ydi百talaudio印plica廿onKeyWords：SigInaDeltaModulation，Analo哥toDi百talconVeners，OperationalTrallceconductanceAmplifier，SigIlaltoNoiseRatio，SwitchcdCapacitorI