外文翻譯--基于dds精密頻率測(cè)量的一種替代方法（英文）

1、Electrical Engineering 81 (1998) 343-349 ?9 Springer-Verlag 1998 An alternative method of precise frequency by the aid of a DDS J. E. Plevridis, J. C. Pliatsikas, C. S. Koukourlis, J. N. Sahalos measurement Contents A me

2、thod of frequency measurement based on a closed loop composed mainly of a Frequency Compar- ator (FC) and a Direct Digital Synthesizer (DDS) is pre- sented in this paper. The DDS serves as reference sinewave signal g

3、enerator acting at one of the FC's inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the comparison of the two signals a logic output that controls an up/down count

4、er is produced. The counter's output acting as the Frequency Setting Word (FSW) instructs the DDS to produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital

5、 estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associate

6、d stages up to the in- strument's display are presented. Ein alternatives Veffahren zur genauen Frequenz- messung mittels eines DD$ 0bersicht Es wird ein Verfahren zur Frequenzmessung vorgestellt, das haupts/ichli

7、ch einen Frequenzkomparator (FC) und einen direkten digitalen Synthesizer (DDS) in geschlossener Schleife entMlt. Der DDS dient als Genera- tor ffir sinusf6rmige Referenzsigale, die auf einen der Eing~inge des FC ein

8、wirken. Der FC vergleicht den Si- gnalverlauf des DDS mit der unbekannten Frequenz und erzeugt ein logisches Signal, welches einen Aufw/irts-/Ab- wiirts-Zghler steuert. Der Zfihlerausgang dient als Fre- quenzsollwert

9、 (FSW) und erzeugt im DDS eine neue, der Meggr6fle beztiglich der Frequenz n/ihere Sinusschwin- gung. Schliefllich gibt der FSW den digitalen Sch~itzwert der zu messenden Frequenz an. Die hohe Aufl6sung des DDS und d

10、ie St6rsicherheit der Schleife erlauben den Aufbau eines hochwertigen Frequenzmessers, dessen ver- schiedene Stufen bis zum Display vorgestellt werden. Received: 20. May 1998 ]. E. Plevridis, ]. C. Pliatsikas, C. S. Ko

11、ukourlis Demokritos University of Thrace, Electrical and Computer Engineering Dept., Telecommunications Systems Laboratory, GR-671 00, Xanthi, Greece I. N. Sahalos Aristotle University of Thessaloniki, Dept. of Phys

12、ics, Radiocommunications Laboratory, GR-540 06, Thessaloniki, Greece Correspondence to: C. S. Koukourlis 1 Introduction The most commonly used frequency measurement tech- nique adopts counters that count the pulses

13、of the un- known frequency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency are counted during one or more periods of the unknown one are also common.

14、In the latter case, the period instead of the frequency is estimated [1]. Some papers [2-6] in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (hea

15、rt) signals (a few hertz) or in the mains frequency (50-60 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In [2], the frequency is

16、calculated by the method of look-up tables. Others [4-6] are microprocessor or microcontroller based. The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefi

17、ned tinle interval and calculate the result after- wards. Its closed-loop form characterizes the proposed method in this paper. By the term “closed-loop“ we denote some sort of feedback. A waveform with a known (con-

18、 trolled) frequency is produced within the circuit and is fed back to the frequency comparison stage which consecu- tively forces it to approximate the unknown (input) fre- quency. The device that produces the above m

19、entioned waveform of controlled frequency is a Direct Digital Syn- thesizer [7, 8]. 2 Direct Digital Synthesis A typical Direct Digital Synthesizer consists of a RaM containing samples of a sinewave (sine look-up ta

20、ble, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which deter- mines the phase step. A typical FSW is 32-bit wide, but 48- bit synthesizers leading in higher freq

21、uency resolution are also available. A phase accumulator produces the succes- sive addresses of the sine look-up table and generates a digitized sine wave output. The digital part of the DDS, the phase accumulator an

22、d the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitiz

23、ed sinewave, producing a continuous output signal. In the applications where a square wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use e.g. the MSB of the accumul

24、ator's output 343 I. E. Plevridis et al.: An alternative method of precise frequency measurement by the aid of a DDS foos Fig. 2. Delay Reset eLK ' )D [ I ~'v'u~' I Edge detector / ? , te

25、r Delay Reset Edge detector vcc Set vce t Reset Detailed Diagram of the Frequency Comparator Block operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circ

26、uit needs some time to realize the correct frequency relation. We will refer to this time as “hysteresis“. Hys- teresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially,

27、 during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The am- biguity settles when two rising edges of the higher fre- quency waveform occur during one pe

28、riod of the lower one. If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the compar- ator's output will toggle, indicating alternatively that the DDS frequency is high

29、er or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage comparator) an equality indication could not exist. In our case this is not a problem because the circuit

30、is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, a

31、s will be explained later. Although an analog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or

32、Programmable Logic Devices (PLDs) with no need of analog components, wide frequency range of operation and shorter response time. 3.2.1 Interaction between frequency comparator and digital synthesizer After the succ

33、essive approximation of the unknown fre- quency the Frequency Comparator “realizes“ that the synthesized frequency is higher (lower) than the unknown one and produces a logic 0 (1) at the output which com- mands the

34、up/down counter to count in the down (up) direction. As previously mentioned, the output of this RS Flip/Flop OUT counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially l

35、ower, the synthesized frequency will increase progressively to reach the unknown one. This will not be “realized“ by the fre- quency comparator and the synthesized frequency will keep on increasing for some clock cyc

36、les, until the com- parator detects the correct relation of it's two input fre- quencies, the unknown one and the DDS output. The same phenomenon will be observed for the opposite (decreas- ing) case also. This i

37、s due to hysteresis that was mentioned earlier. When DDS output (]CDDs) has approached ~n, due to hysteresis, no specific frequency is synthesized. Instead, it swings between fl and f2, where fl and f2 are the two ex-

38、 treme values of the frequency swing lying symmetrically around J~n. The DDS output can be considered as a fre- quency modulated carrier by a triangular waveform. The triangular waveform is the analog representation

39、of the FSW applied to the DDS. Fig. 3a, lower trace shows a typical output of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the corre

40、ct value. This waveform has been captured using an auxiliary hardware circuit: A digital-to-analog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is no

41、t shown in the block diagram of the circuit. Stated differently, the lower trace of Fig. 3a is the U/D command (input) to the counter while the upper trace is a hypothetical “frequency modulating“ waveform. It is obv

42、ious that the term “hypothetical“ is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope o

43、f the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is +k ?