數(shù)字頻率計(jì)的介紹畢業(yè)論文外文翻譯

1、<p><b>　　學(xué) 位 論 文</b></p><p>　　太原工業(yè)學(xué)院學(xué)位論文英文翻譯</p><p>　　作 者 姓 名： </p><p>　　學(xué)科、專業(yè) ： 通信工程 </p><p>　　學(xué) 號(hào) ： <

2、/p><p>　　指 導(dǎo) 教 師： </p><p>　　完 成 日 期： </p><p><b>　　英文原文：</b></p><p>　　Introduction of digital frequency meter</p><p>　　Digital

3、 Frequency of communications equipment, audio and video, and other areas of scientific research and production of an indispensable instrument. Programming using Verilog HDL Design and Implementation of the digital freque

4、ncy, in addition to the plastic part of the measured signal, and digital key for a part of the show, all in an FPGA chip to achieve. The entire system is very lean, flexible and have a modification of the scene.</p>

5、;<p>　　1 And other precision measuring frequency Principle.</p><p>　　Frequency measurement methods can be divided into two kinds: (1) direct measurement method, that is, at a certain time measur

6、ement gate measured pulse signal number. (2) indirect measurements, such as the cycle frequency measurement, VF conversion law. Frequency Measurement indirect measurement method applies only to low-frequency signal

7、s.</p><p>　　Based on the principles of traditional frequency measurement of the frequency of measurement accuracy will be measured with the decline in signal frequency decreases in the more practical limitat

8、ions, such as the accuracy and frequency of measurement not only has high accuracy, but also in the whole frequency region to maintain constant test accuracy. The main method of measurement frequency measurement Preferen

9、ces gated signal GATE issued by the MCU, GATE time width on the frequency measurement</p><p>　　2 Frequency of achieving</p><p>　　Frequency Measurement accuracy of such method. Can be simplified

10、as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counte

11、r in the CEN input as enable end, used to control the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flip-flop input, launched at the sa</

12、p><p>　　3And the median frequency of relevant indicators</p><p>　　Median: At the same time the figures show that up to the median. The usual eight-count frequency of only several hundred yuan can b

13、uy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high.      Overflow of:-the ability to promote itself to overflow the equivalent of the total. Some of

14、 the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the purpose of the median. Here</p><p>　　4 Time and Frequency Measure

15、ment</p><p>　　Compared to traditional methods of circuit design, EDA technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilog HDL

16、 description of a multi-level system hardware functions, and support top-down design features. Designers can not understand the hardware structure. Start from the system design, on the top floor of a system block diagram

17、 of the structure and design, in a diagram with Ver-ilog HDL acts on the circuit descri</p><p>　　In the time-frequency measurement method, the multi-cycle synchronization is a high precision, but still unres

18、olved ± a word error, mainly because of the actual gate edge and standard frequency synchronization is not filling pulse edge Tx=N0T0-△t2+△t1, if accurately measured short interval Δ t1 and Δ t2, will be able to acc

19、urately measure time intervals Tx, eliminating ± a word counting error, so as to further enhance accuracy.      To measure a short time interval Δ t1 and Δ t2, commonly used </p><p>

20、;　　Delay quantitative thinking depend on the realization of the delay stability delay unit, the unit depends on the resolution of the delay time delay element.      Delay device as a unit can be pass

21、ive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate delay time longer. Taking into account delays can be predictive ability

22、final choice of the CPLD devices, the realization of the short time interval measur</p><p>　　It has been anal yzed,multi-cycle synchronization frequency measurement, the measurement uncertainty:   

23、;   When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of ±1×10-7/s. When the measurement and quantification of delay circuit with short intervals combined, the uncertainty of mea

24、surement can be derived from the following.     In the use of cycle synchronization, multi-analyte Tx for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+△t1-△<

25、/p><p>　　5 Frequency of VHDL Design</p><p>　　ALTERA use of the FPGA chip EPF10K10 companies, the use of VHDL programming language design accuracy of frequency, given the core course, ISPEXPER simul

26、ation, design verification is successful, to achieve the desired results. Compared to the traditional frequency, the frequency of FPGA simplify the circuit board design, increased system design and the realization of rel

27、iability, frequency measurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital logi</p><p>　　This design uses the AL TERA EPF10K10 FPGA chip, the chip pin the del

28、ay of 5 ns, frequency of 200 MHz, the standardization of application VHDL hardware description language has a very rich data types, the structure of the model is hierarchical, The use of these rich data types and levels

29、of the structure model of a complex digital system logic design and computer simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the d</p>

30、;<p>　　----------------------from Vin Skahill.VHDL for Programmable Logic page76-88</p><p>　　VHDL Design Flow</p><p>　　It's useful to understand the overall VHDL design environment b

31、elbre jumping inlo the language itself. Thew aw several steps in a VHDL- based design process, often called the deign flow. These steps are applicable to any HDL- based design process and are outlined in Figure 1.</p&

32、gt;<p><b>　　front-end</b></p><p><b>　　steps</b></p><p>　　(painful,but no uncommon)</p><p>　　(very painful!)</p><p><b>　　back-end<

33、;/b></p><p><b>　　steps</b></p><p>　　P.1 Steps in a VHDL or other HDL-based design flow</p><p>　　The so-called "flont end" begins with figuring out the basic

34、 approach and building blocks at the block-diagram level. Large logic design, like software programs, are usually hierarchical, and VHDL gives you a good famework for defining modules and their interfaces and filling in

35、the details later.</p><p>　　The next step is the actual writing of VHDL code for modules, their interfaces, and their internal details. Since VHDL is a text-based language, in principle you can use any text

36、editor for this part of the job. However, most design environments include a specialized VHDL text editor that makes the job a little easier; Such editors include features like automatic highlighting of VHDL keywords, au

37、tomatic indenting, built-in templates for frequently used plogram structures, and built-in syntax che</p><p>　　Once you've written some code, you will want to compile it, of course. A VHDL compiler analy

38、zes your code for syntax errors and also checks it for compatibility with other modules on which it relies. It also creates the inlternal information that is needed for a simulator to process your design later. As in oth

39、er programming endeavors, you probably shouldn't wait until the very end of coding to compile all of your code. Doing a piece at a time can prevent you from proliferating syntax errors,inc</p><p>　　Perha

40、ps the most satisfying step come next-simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its kind you might do as homework in a digital-design class, you would probably gener

41、ate inputs and observe outputs manually. But for larger projects, VHDL gives you tile ability to create "test benches" that automatically apply inputs and compare them with expected outputs.</p><p>

42、;　　Actually, simulation is just one piece of a larger step called verification Sure,it is satisfying to watch your simulated circuit produce simulated outputs, but the purpose of simulation is larger -it is to verify tha

43、t tle circuit works as desired. In a typical large project, a substantial amount of effort is expended both during and after the coding stage to define test cases that exercise the circuit over a wide range of logical op

44、erating conditions. Finding design bugs at this stage has a hig</p><p>　　Note that there are at least two dimensions to verification. In functional verification, we study the circuit's logical operation

45、independent of timing considerations; gate delays and other timing parameters are considered to be zero. In timing verification, we study the circuit's operation including estimated sequential devices like flip-flops

46、 are met. It is customary to perform thorough functional verification before starting the back-end steps. However, our ability to do timing verification a</p><p>　　After verification, we are ready to move in

47、to the "back-end" stage The nature of and tools for this stage vary somewhat, depending on the target technology for the design, but there are three basic steps. The first is synthesis, converting the VHDL desc

48、ription into a set of primitives or components that call be assembled in the target technology. For example, with PLD or CPLD, the synthesis tool may generate two-level sum-of-products equations .With ASIC, it may genera

49、te a Iist of gates and a ne</p><p>　　In the fitting step, a fitting tool or fitter maps the synthesized primitives or components onto available AND-OR elements For an ASIC. it may mean laying down individua

50、l gates in a pattern and finding ways to connect them within the physical constraints of the ASIC die: this is called the place-and-route process. The designer can usually specify additional constraints at this stage, su

51、ch as the placement of modules with a chip or the pin assignments of extrnal input and output</p><p><b>　　pins.</b></p><p>　　The "final” step is timing verification of the fitte

52、d circuit It is only at this stage that the actual circuit delays due to wire lengths, electrical loading, and other factors can be calculated with reasonable precision. It is usual during this step to apply the same tes

53、t cases that were used in functional verification, but in this step they are run against the circuit as if will actually be built.</p><p>　　As in any other creative process, you may occasionally take two ste

54、ps forword and one step back (or worse!) As suggested in the figure, during coding you may encounter problems that force you to go back and rethink your hierarchy, and you will almost certainly have compilation and simul

55、ation errors that force you to rewrite parts of the code.</p><p>　　The most painful problems am the ones that you encounter in the back end of the design flow .For example, if the synthesized design doesn&#

56、39;t fit into an available FPGA or doesn't meet timing requirements, you may have to go back as far as rethinking your whole design approach. That's worth rememberlng- excellent tooIs are still no substitute for

57、careful thought at the outset of a design.</p><p>　　----------------------from Volnei A.Pedroni.Circuit Design with VHDL page3-5</p><p><b>　　中文譯文：</b></p><p><b>　

58、　數(shù)字頻率計(jì)的介紹</b></p><p>　　數(shù)字頻率計(jì)是通信設(shè)備、音、視頻等科研生產(chǎn)領(lǐng)域不可缺少的測(cè)量?jī)x器。采用Verilog HDL編程設(shè)計(jì)實(shí)現(xiàn)的數(shù)字頻率計(jì)，除被測(cè)信號(hào)的整形部分、鍵輸入部分和數(shù)碼顯示部分外，其余全部在一片F(xiàn)PGA芯片上實(shí)現(xiàn)。整個(gè)系統(tǒng)非常精簡(jiǎn)，且具有靈活的現(xiàn)場(chǎng)可更改性。</p><p><b>　　1 等精度測(cè)頻原理</b></

59、p><p>　　頻率的測(cè)量方法主要分為2 種方法:</p><p>　　(1) 直接測(cè)量法, 即在一定的閘門時(shí)間內(nèi)測(cè)量被測(cè)信號(hào)的脈沖個(gè)數(shù)。</p><p>　　(2) 間接測(cè)量法, 例如周期測(cè)頻法、V F 轉(zhuǎn)換法等。間接測(cè)頻法僅適用測(cè)量低頻信號(hào)。</p><p>　　基于傳統(tǒng)測(cè)頻原理的頻率計(jì)的測(cè)量精度將隨被測(cè)信號(hào)頻率的下降而降低, 在實(shí)用中有較大

60、的局限性, 而等精度頻率計(jì)不但具有較高的測(cè)量精度, 而且在整個(gè)頻率區(qū)域能保持恒定的測(cè)試精度。頻率測(cè)量方法的主要測(cè)量預(yù)置門控信號(hào)GATE是由單片機(jī)發(fā)出，GATE的時(shí)間寬度對(duì)測(cè)頻精度影響較少，可以在較大的范圍內(nèi)選擇，只要FPGA中32 b計(jì)數(shù)器在計(jì)100 M信號(hào)不溢出都行，根據(jù)理論計(jì)算GATE的時(shí)間寬度Tc可以大于42．94 s，但是由于單片機(jī)的數(shù)據(jù)處理能力限制，實(shí)際的時(shí)間寬度較少，一般可在10～0．1 s間選擇，即在高頻段時(shí)，閘門時(shí)間較短

61、；低頻時(shí)閘門時(shí)間較長(zhǎng)。這樣閘門時(shí)間寬度Tc依據(jù)被測(cè)頻率的大小自動(dòng)調(diào)整測(cè)頻，從而實(shí)現(xiàn)量程的自動(dòng)轉(zhuǎn)換，擴(kuò)大了測(cè)頻的量程范圍；實(shí)現(xiàn)了全范圍等精度測(cè)量，減少了低頻測(cè)量的誤差。</p><p>　　本設(shè)計(jì)頻率測(cè)量方法的主要測(cè)量控制框圖如圖1 所示。圖1 中預(yù)置門控信號(hào)GA TE 是由單片機(jī)發(fā)出, GA TE的時(shí)間寬度對(duì)測(cè)頻精度影響較少, 可以在較大的范圍內(nèi)選擇, 只要FPGA 中32 b 計(jì)數(shù)器在計(jì)100M 信號(hào)不溢出都行

62、, 根據(jù)理論計(jì)算GA TE 的時(shí)間寬度T c 可以大于42194s, 但是由于單片機(jī)的數(shù)據(jù)處理能力限制, 實(shí)際的時(shí)間寬度較少, 一般可在10～ 011 s 間選擇, 即在高頻段時(shí), 閘門時(shí)間較短; 低頻時(shí)閘門時(shí)間較長(zhǎng)。這樣閘門時(shí)間寬度T c 依據(jù)被測(cè)頻率的大小自動(dòng)調(diào)整測(cè)頻, 從而實(shí)現(xiàn)量程的自動(dòng)轉(zhuǎn)換, 擴(kuò)大了測(cè)頻的量程范圍; 實(shí)現(xiàn)了全范圍等精度測(cè)量, 減少了低頻測(cè)量的誤差。</p><p><b>　　2

63、 頻率計(jì)的實(shí)現(xiàn)</b></p><p>　　等精度測(cè)頻的實(shí)現(xiàn)方法 ?？珊?jiǎn)化為CNT1和CNT2是兩個(gè)可控計(jì)數(shù)器，標(biāo)準(zhǔn)頻率(f )信號(hào)從CN F1的時(shí)鐘輸入端cI K輸入，經(jīng)整形后的被測(cè)信號(hào)(f )從CNT2的時(shí)鐘輸入端cI K輸入。每個(gè)計(jì)數(shù)器中的CEN輸入端為使能端，用來(lái)控制計(jì)數(shù)器計(jì)數(shù)。當(dāng)預(yù)置閘門信號(hào)為高電平(預(yù)置時(shí)間開始)時(shí)。被測(cè)信號(hào)的上升沿通過(guò)D觸發(fā)器的輸入端，同時(shí)啟動(dòng)兩個(gè)汁數(shù)器計(jì)數(shù)；同樣，當(dāng)預(yù)置

64、閘門信號(hào)為低電平(預(yù)置時(shí)間結(jié)束)時(shí)，被測(cè)信號(hào)的上升沿通過(guò)D觸發(fā)器的輸出端，使計(jì)數(shù)器停止計(jì)數(shù)。</p><p>　　3 頻率計(jì)的位數(shù)及相關(guān)指標(biāo) </p><p>　　位數(shù)：同時(shí)最多能顯示的數(shù)字位數(shù)。平常計(jì)數(shù)式的8位頻率計(jì)只有幾百元就可買到。對(duì)于高精度的測(cè)量，9位剛剛開始，11位算中等，13位才能算比較高級(jí)。 </p><p>　　溢出位：把溢出位算進(jìn)去的總等效位。有些

65、頻率計(jì)帶有溢出功能，即把最高位溢出不顯示而只顯示后面的位，以便達(dá)到提高位數(shù)的目的。這里個(gè)別指標(biāo)是估計(jì)值。 </p><p>　　速度：即每秒能出多少位。有了高位數(shù)的但測(cè)量特別慢也失去了意義。平常計(jì)數(shù)式的8位頻率計(jì)，測(cè)量10MHz信號(hào)、1秒閘門能得到10,000,000Hz，這實(shí)際上才是7位（位數(shù)等于取常用對(duì)數(shù)后的值），要想得到8位，需要10秒閘門；要想得到9位，需要100秒閘門，依次類推，即便顯示允許，11位需要

66、10000秒的測(cè)量時(shí)間了。但無(wú)論如何，還是每秒7位。因此，要想快速得到高位數(shù)則必須高速度。 </p><p>　　分辨：這就像一個(gè)電壓表最小可以分辨出多大的電壓的指標(biāo)是類似的，越小越好，單位ps（皮秒）。1000ps=1ns。假設(shè)你用1ns的頻率計(jì)要分辨出1e-12的誤差，就需要1ns/1e-12=1000秒的時(shí)間。而假設(shè)你有另外一個(gè)頻率計(jì)的分辨是100ps，那么測(cè)量時(shí)間就可以縮短10倍為100秒，或者可以在相同

67、的1000秒下測(cè)量出1e-14的誤差。</p><p><b>　　4 時(shí)間頻率測(cè)量</b></p><p>　　相比傳統(tǒng)的電路系統(tǒng)設(shè)計(jì)方法，EDA技術(shù)采用VHDL語(yǔ)言描述電路系統(tǒng)，包括電路的結(jié)構(gòu)、行為方式、邏輯功能及接口。Verilog HDL具有多層次描述系統(tǒng)硬件功能的能力，支持自頂向下的設(shè)計(jì)特點(diǎn)。設(shè)計(jì)者可不必了解硬件結(jié)構(gòu)。從系統(tǒng)設(shè)計(jì)入手，在頂層進(jìn)行系統(tǒng)方框圖的劃

68、分和結(jié)構(gòu)設(shè)計(jì)，在方框圖一級(jí)用Ver-ilog HDL對(duì)電路的行為進(jìn)行描述，并進(jìn)行仿真和糾錯(cuò)，然后在系統(tǒng)一級(jí)進(jìn)行驗(yàn)證，最后再用邏輯綜合優(yōu)化工具生成具體的門級(jí)邏輯電路的網(wǎng)表，下載到具體的FPGA器件中去，從而實(shí)現(xiàn)FPGA的設(shè)計(jì)。</p><p>　　時(shí)間頻率測(cè)量是電子測(cè)量的重要領(lǐng)域。頻率和時(shí)間的測(cè)量已越來(lái)越受到重視，長(zhǎng)度、電壓等參數(shù)也可以轉(zhuǎn)化為與頻率測(cè)量有關(guān)的技術(shù)來(lái)確定。本文通過(guò)對(duì)傳統(tǒng)的多周期同步法進(jìn)行探討，提出了多

69、周期同步法與量化時(shí)延法相結(jié)合的測(cè)頻方法。 </p><p>　　最簡(jiǎn)單的測(cè)量頻率的方法是直接測(cè)頻法。直接測(cè)頻法就是在給定的閘門信號(hào)中填入脈沖，通過(guò)必要的計(jì)數(shù)電路，得到填充脈沖的個(gè)數(shù)，從而算出待測(cè)信號(hào)的頻率或周期。在直接測(cè)頻的基礎(chǔ)上發(fā)展的多周期同步測(cè)量方法，在目前的測(cè)頻系統(tǒng)中得到越來(lái)越廣泛的應(yīng)用。多周期同步法測(cè)頻技術(shù)的實(shí)際閘門時(shí)間不是固定的值，而是被測(cè)信號(hào)的整周期倍，即與被測(cè)信號(hào)同步，因此消除了對(duì)被測(cè)信號(hào)計(jì)數(shù)時(shí)產(chǎn)生

70、的±1個(gè)字誤差，測(cè)量精度大大提高，而且達(dá)到了在整個(gè)測(cè)量頻段的等精度測(cè)量，</p><p>　　在時(shí)頻測(cè)量方法中，多周期同步法是精度較高的一種，但仍然未解決±1個(gè)字的誤差，主要是因?yàn)閷?shí)際閘門邊沿與標(biāo)頻填充脈沖邊沿并不同步</p><p>　　Tx=N0T0-△t2+△t1，如果能準(zhǔn)確測(cè)量出短時(shí)間間隔Δt1和Δt2，也就能夠準(zhǔn)確測(cè)量出時(shí)間間隔Tx，消除±1個(gè)字的計(jì)

71、數(shù)誤差，從而進(jìn)一步提高精度。</p><p>　　為了測(cè)量短時(shí)間間隔Δt1和Δt2，通常使用模擬內(nèi)插法或游標(biāo)法與多周期同步法結(jié)合使用，雖然精度有很大提高，但終未能解決±1個(gè)字的誤差這個(gè)根本問題，而且這些方法設(shè)備復(fù)雜，不利于推廣。</p><p>　　要得到精度高，時(shí)間響應(yīng)快，結(jié)構(gòu)簡(jiǎn)單的頻率和時(shí)間測(cè)量方法是比較困難的。</p><p>　　從結(jié)構(gòu)盡量簡(jiǎn)單同時(shí)

72、兼顧精度的角度出發(fā)，將多周期同步法與基于量化時(shí)延的短時(shí)間間隔測(cè)量方法結(jié)合，實(shí)現(xiàn)了寬頻范圍內(nèi)的等精度高分辨率測(cè)量。</p><p>　　量化時(shí)延法測(cè)短時(shí)間間隔 </p><p>　　光電信號(hào)可以在一定的介質(zhì)中快速穩(wěn)定的傳播，且在不同的介質(zhì)中有不同的延時(shí)。通過(guò)將信號(hào)所產(chǎn)生的延時(shí)進(jìn)行量化，實(shí)現(xiàn)了對(duì)短時(shí)間間隔的測(cè)量。</p><p>　　其基本原理是“串行延遲，并行計(jì)數(shù)”

73、，而不同于傳統(tǒng)計(jì)數(shù)器的串行計(jì)數(shù)方法，即讓信號(hào)通過(guò)一系列的延時(shí)單元，依靠延時(shí)單元的延時(shí)穩(wěn)定性，在計(jì)算機(jī)的控制下對(duì)延時(shí)狀態(tài)進(jìn)行高速采集與數(shù)據(jù)處理，從而實(shí)現(xiàn)了對(duì)短時(shí)間間隔的精確測(cè)量。</p><p>　　量化時(shí)延思想的實(shí)現(xiàn)依賴于延時(shí)單元的延時(shí)穩(wěn)定性，其分辨率取決于單位延時(shí)單元的延遲時(shí)間。</p><p>　　作為延時(shí)單元的器件可以是無(wú)源導(dǎo)線，有源門器件或其他電路。其中，導(dǎo)線的延遲時(shí)間較短(接近光

74、速傳播的延遲)，門電路的延遲時(shí)間相對(duì)較長(zhǎng)?？紤]到延遲可預(yù)測(cè)能力，最終選擇了CPLD器件，實(shí)現(xiàn)對(duì)短時(shí)間間隔的測(cè)量。 </p><p>　　將短時(shí)間間隔的開始信號(hào)送入延時(shí)鏈中傳播，當(dāng)結(jié)束信號(hào)到來(lái)時(shí)，將此信號(hào)在延時(shí)鏈中的延時(shí)狀態(tài)進(jìn)行鎖存，通過(guò)CPU讀取，判斷信號(hào)經(jīng)過(guò)的延時(shí)單元個(gè)數(shù)就可以得到短時(shí)時(shí)間間隔的大小，分辨率決定于單位延時(shí)單元的延時(shí)時(shí)間。</p><p>　　一般來(lái)講，為了測(cè)量?jī)蓚€(gè)短時(shí)間間

75、隔，使用兩組延時(shí)和鎖存模塊，但實(shí)際上，給定的軟件閘門時(shí)間足夠大，允許CPU完成取數(shù)的操作，即能夠在待測(cè)時(shí)間間隔結(jié)束之前取走短時(shí)間隔Δt1對(duì)應(yīng)的延時(shí)單元的個(gè)數(shù)，通過(guò)一定的控制信號(hào)，可以只用一組延時(shí)和鎖存單元，這樣可以節(jié)省CPLD內(nèi)部的資源。利用多周期同步與量化時(shí)延相結(jié)合的方法，計(jì)算公式為：</p><p>　　T=n0t0+n1t1-n2t1 </p><p>　　上式中，n0為對(duì)填充脈沖的

76、計(jì)數(shù)值；t0為填充脈沖的周期，即100ns；n1為短時(shí)間隔Δt1對(duì)應(yīng)的延時(shí)單元的個(gè)數(shù)；n2為短時(shí)間隔Δt2對(duì)應(yīng)的延時(shí)單元的個(gè)數(shù)；t1為量化延遲器件延時(shí)單元的延遲量(4.3ns)。 這樣，利用多周期同步法，實(shí)現(xiàn)了閘門和被測(cè)信號(hào)同步；利用量化時(shí)延法，測(cè)量了原來(lái)測(cè)不出來(lái)的兩個(gè)短時(shí)間間隔，從而準(zhǔn)確地測(cè)量了實(shí)際閘門的大小，也就提高了測(cè)頻的精度。</p><p>　　由于頻率合成器輸出的頻率信號(hào)最小只能調(diào)到10Hz，把X

77、DU-17的測(cè)量值作為標(biāo)準(zhǔn)，可以計(jì)算出樣機(jī)測(cè)頻的精度。</p><p>　　例如，被測(cè)信號(hào)為15.000010MHz時(shí)被測(cè)信號(hào)為5.00001002MHz時(shí)，從上面的計(jì)算可以看出，樣機(jī)的分辨率已達(dá)ns量級(jí)，下面從理論分析的角度來(lái)說(shuō)明這一點(diǎn)。</p><p>　　前面已經(jīng)分析過(guò)，多周期同步法測(cè)頻時(shí)，它的測(cè)量不確定度為：</p><p>　　當(dāng)輸入f0為10MHz，閘門

78、時(shí)間為1s時(shí)，測(cè)量的不確定度為±1×10-7/s。當(dāng)與量化延時(shí)測(cè)量與短時(shí)間間隔電路相結(jié)合時(shí)，測(cè)量的不確定度可以從下述推導(dǎo)出來(lái)。</p><p>　　在采用多周期同步法時(shí)，Tx為待測(cè)的多周期值，T0為采用的時(shí)基周期。</p><p>　　Tx= NT0+△t1-△t2 </p><p>　　與量化延時(shí)電路相結(jié)合后有：</p><

79、p>　　Tx= NT0+(N1-N2)td±δTx </p><p>　　這里，δTx為測(cè)量的不準(zhǔn)確度。</p><p>　　對(duì)上式微分得： \δTx≤±2td </p><p>　　由上式可知，此方法的測(cè)量精度取決于td，它的穩(wěn)定性與大小直接影響測(cè)量值的不確定度。所以采用各種方法，計(jì)數(shù)器可在整個(gè)頻率量程內(nèi)實(shí)現(xiàn)等精度的測(cè)量，而且測(cè)量精度有顯

80、著提高，測(cè)量分辨率提高到4.3ns，且消除了±1個(gè)字的理論誤差，精度提高了20多倍。</p><p>　　結(jié)束語(yǔ) 本文將給出了一種新的測(cè)頻方法。基于此方法的頻率計(jì)的數(shù)字電路部分集成在一片CPLD中，大大減小了整個(gè)儀器的體積，提高了可靠性，且達(dá)到了很高的測(cè)量分辨率。</p><p>　　5 頻率計(jì)的VHDL 設(shè)計(jì)</p><p>　　利用ALTERA公司

81、的FPGA芯片EPF10K10，使用VHDL編程語(yǔ)言設(shè)計(jì)等精度頻率計(jì)，給出核心程序，經(jīng)過(guò)ISPEXPER仿真后，驗(yàn)證設(shè)計(jì)是成功的，達(dá)到預(yù)期結(jié)果。傳統(tǒng)的頻率計(jì)相比，F(xiàn)PGA的頻率計(jì)簡(jiǎn)化了電路板的設(shè)計(jì)，提高了系統(tǒng)設(shè)計(jì)的實(shí)現(xiàn)性和可靠性，測(cè)頻范圍達(dá)到100 MHz，實(shí)現(xiàn)了數(shù)字系統(tǒng)硬件的軟件化，這是數(shù)字邏輯設(shè)計(jì)的新趨勢(shì)。</p><p>　　本設(shè)計(jì)采用AL TERA 公司的FPGA 芯片EPF10K10, 該芯片管腳間的延

82、遲為5 ns, 即頻率為200MHz, 應(yīng)用標(biāo)準(zhǔn)化的硬件描述語(yǔ)言VHDL 有非常豐富的數(shù)據(jù)類型, 他的結(jié)構(gòu)模型是層次化的, 利用這些豐富的數(shù)據(jù)類型和層次化的結(jié)構(gòu)模型, 對(duì)復(fù)雜的數(shù)字系統(tǒng)進(jìn)行邏輯設(shè)計(jì)并用計(jì)算機(jī)仿真, 逐步完善后進(jìn)行自動(dòng)綜合生成符合要求的、在電路結(jié)構(gòu)上可實(shí)現(xiàn)的數(shù)字邏輯, 再下載到可編程邏輯器件中, 即可完成設(shè)計(jì)任務(wù)。</p><p>　　--------------譯自文斯凱赫爾著的VHDL邏輯設(shè)計(jì)7

83、6-88頁(yè)</p><p><b>　　VHDL設(shè)計(jì)流程</b></p><p>　　在深入了解VHDL語(yǔ)言之前．先理解VHDL設(shè)計(jì)環(huán)境是很有幫助的。基于VHDL的設(shè)計(jì)過(guò)程有幾個(gè)步驟，通常稱為設(shè)計(jì)流程。這些步驟適用于何基于硬件描述晤言的設(shè)計(jì)過(guò)程，由圖.1概略表示。</p><p><b>　　前</b></p>

84、<p><b>　　端 </b></p><p><b>　　步</b></p><p><b>　　驟</b></p><p>　　(雖然是痛苦的，但是很平常)</p><p>　　后 (很痛苦的!)</p><p><b&g

85、t;　　端</b></p><p><b>　　步</b></p><p><b>　　驟</b></p><p>　　圖1.VHDL或其它基于HDL的設(shè)計(jì)流程步驟</p><p>　　所謂的“前端”步驟，就是從方框圖層次上寫出基本方法和結(jié)構(gòu)快。像軟件程序那樣的大的邏輯設(shè)計(jì)通常是分層次的

86、，VHDL給出了很好的框架用于定義模塊及其界面，細(xì)節(jié)內(nèi)容隨后再填充。</p><p>　　下一步是實(shí)際寫出模塊，界面，及其內(nèi)部細(xì)節(jié)的VHDL代碼。由于VHDL是基于文本的語(yǔ)言，原則上可以用任何文本編輯器完成這部分工作。然而，大多數(shù)設(shè)計(jì)環(huán)境包括特別的VHDL文本編輯器，使得工作更簡(jiǎn)單些。這樣的編輯器有一些特點(diǎn)，例如，VHDL關(guān)鍵詞的突出顯示，自動(dòng)縮進(jìn)，常用程序結(jié)構(gòu)的內(nèi)置模板，內(nèi)置語(yǔ)法檢查和編譯器快速啟動(dòng)。</

87、p><p>　　一旦寫出某個(gè)代碼，你就想編譯它，VHDL語(yǔ)法編譯器會(huì)分析你的代碼有沒有語(yǔ)法錯(cuò)誤，并檢查它與其它模塊的兼容性。它還用于處理設(shè)計(jì)的模擬器所需要的內(nèi)部信息。像其它編程工作一樣，你可能不想等到所有的代碼編譯完。一次做一點(diǎn)，可防止擴(kuò)散語(yǔ)法錯(cuò)誤以及不一致命名，等等，而且在完成項(xiàng)目之前就給你一種“欲罷不能”的感覺。</p><p>　　下一步是模擬，這也許是最滿意的步驟，VHDL模擬器允許你

88、定義輸入并應(yīng)用到設(shè)計(jì)中去，同時(shí)觀察輸出而不必建立物理電路。在小型項(xiàng)目中，如在數(shù)學(xué)設(shè)計(jì)課上的作業(yè)，你可以手工產(chǎn)生輸入并與預(yù)期的輸出比較。</p><p>　　實(shí)際上，模擬只是被稱為驗(yàn)證的一部分，當(dāng)然，看到模擬的電路產(chǎn)生輸出是令人滿意的，但模擬的目的要更高些，它要驗(yàn)證電路是否按預(yù)期的那樣工作。在典型的大型項(xiàng)目中，在編碼過(guò)程中和之后，都需要做大量的動(dòng)作來(lái)定義很寬范圍的邏輯操作條件，以及在這些條件下電路運(yùn)行的測(cè)試情況。在

89、這個(gè)步驟如能找出設(shè)計(jì)上的問題，是很有用的，如果在以后才找到問題，則通常必須重新做所有的“后端“步驟。</p><p>　　要注意，至少有兩個(gè)方面的問題需要驗(yàn)證。在功能驗(yàn)證中，主要研究不考慮定地條件下的邏輯操作，門延遲和其它定時(shí)參數(shù)都讓認(rèn)為是零。在定時(shí)驗(yàn)證中主要研究包含了估算延遲的電路操作，驗(yàn)證如觸發(fā)器這樣的時(shí)序器件的建立，保持以及其它的定時(shí)要求。按慣例，在開始“后端”步驟前，要充分做好功能驗(yàn)證。但是，在這一步做定

90、時(shí)驗(yàn)證通常是受限制的，因?yàn)闀r(shí)序行為非常依賴于綜合以及擬合的結(jié)果。我們可以做些初步的定時(shí)驗(yàn)證，以獲得全部設(shè)計(jì)過(guò)程中的一些安慰，但具體的定時(shí)驗(yàn)證必須到最后才能做。</p><p>　　驗(yàn)證之后，就可以進(jìn)行“后端”的工作了。這一步驟的性質(zhì)和用到得工具，依據(jù)設(shè)計(jì)的目標(biāo)技術(shù)會(huì)有些不同，但仍可分為三個(gè)基本的步驟。第一步為綜合，就是將VHDL的描述轉(zhuǎn)換成能在目標(biāo)技術(shù)中使用的基本元素和部件的集合。例如，用PLD或者CPLD，綜合

91、工具可產(chǎn)生兩極“與-或”等式，用ASIC將產(chǎn)生一個(gè)門電路的列表以及一個(gè)網(wǎng)表，用來(lái)指定門之間的如何互聯(lián)。設(shè)計(jì)者可提供一些技術(shù)上的約束條件來(lái)“幫助”綜合工具，如邏輯層次的最大數(shù)或所用邏輯緩沖器的強(qiáng)度。</p><p>　　在擬合步驟，擬合工具將被綜合的原始或元件映射到可得到的器件資源上。對(duì)于PLD或CPLD，這可能意味著將等式轉(zhuǎn)化為可行的“與-或”元件。對(duì)于ASIC，它可能意味著以一定模式放置各個(gè)門，并找出在ASIC

92、模片的物理約束條件，各個(gè)門的連接方法，這稱為布局與布線。在這個(gè)階段，設(shè)計(jì)者通?？梢蕴岢鲱~外的約束條件，如模塊在芯片中的布局或外部輸入輸出引腳的分配。</p><p>　　“最后”的步驟是被擬合的電路的定時(shí)驗(yàn)證，只有在這一步，由于邊線長(zhǎng)度，電氣負(fù)載其他因素引起的時(shí)基電路延遲，才以合適的精度進(jìn)行計(jì)算。通常這一步使用了和驗(yàn)證一樣的測(cè)試條件，但這一步它們是按照實(shí)際構(gòu)成的電路來(lái)運(yùn)行的。</p><p&g

93、t;　　跟任何其它創(chuàng)造性過(guò)程一樣，你可能會(huì)偶爾前進(jìn)在后退半步（或者更糟）。如圖所示，你可能在編碼時(shí)遇到的一些問題，迫使你回頭并重新考慮層次結(jié)構(gòu)，你完全可能遇到編譯或模擬錯(cuò)誤使你重寫部分代碼。</p><p>　　最痛苦的問題是在設(shè)計(jì)流程的后端遇到的。例如，若綜合的設(shè)計(jì)不適于可行的FPGA或不符合定時(shí)的要求，你可能不得不重新考慮整個(gè)設(shè)計(jì)。值得記住的是：出色的工具并不能代替設(shè)計(jì)之初的細(xì)心籌謀。</p>