h.264編碼算法在雙核dsp上的實現(xiàn)方法研究

1、華中科技大學碩士學位論文H.264編碼算法在雙核DSP上的實現(xiàn)方法研究姓名：王全明申請學位級別：碩士專業(yè)：計算機系統(tǒng)結構指導教師：陳加忠20070604II 華 中 科 技 大 學 碩 士 學 位 論 文 Abstract* Compare with all previous video encoding standards, H.264 has higher encoding efficiency. However, the hig

2、her encoding efficiency is based on the increase of computational complexity. The higher complexity has affected the industrialization process of H.264 to some extent. Many companies and research institutions try their b

3、est to explore the real-time solution of H.264 Encoder in embedded system, especially in DSP (Digital Signal Processor) platform. However, as the high complexity and the resources limitation of the embedded system, there

4、 has no good solution up to now. In allusion to the system architecture of ADSP-BF561 of ADI (Analog Devices Incorporation) and the characteristics of the H.264 encoding algorithm, transform, quantization, de-quantizatio

5、n, inverse transform, entropy coding and loop filter, border expansion, half Pixel interpolation were assigned to both of the Cores of ADSP-BF561, respectively, and Cache and DMA (Direct Memory Access) were choosing as t

6、he data scheduling strategy. Meanwhile, code optimization has eased the DSP resource constraints to some extent. Finally, a complexity reduction algorithm for motion estimation is proposed. The proposed algorithm can ach

7、ieve computational savings of 8.33%–33.33% (depending on the source video sequence) with no significant loss of rate-distortion performance. Simulation results demonstrate that the optimized H.264 Encoder achieve higher

8、encoding frame rate (up to 30 fps) for the video sequece of CIF (352×288) format with no significant loss of rate-distortion performance. However, it need for further study and optimization for the video sequece of

9、VGA (640×480) format. Key words: Video Encoding, DSP, H.264, ADSP-BF561, Dual Core * This work is supported by the foundation of nature science of Hu Bei Province: The research of adaptively selecting of the transf