layout design and verification of the voltage reference module in the auto electronic ignition contr

1、<p>　　Layout Design and Verification of the Voltage Reference Module in the Auto Electronic Ignition Contr</p><p>　　Abstract： This article describes the layout design and verification of the input modul

2、e of a auto electronic ignition chip used in the field of automotive engineering. Using standard bipolar technology， full-custom design on the input module placement and routing， and completed the back-end verification.

3、This chip has low power consumption， low cost， and stable performance. </p><p>　　Key words： Auto electronic ignition chip， Layout design </p><p>　　1 Introduction </p><p>　　Auto elec

4、tronic ignition control chip is designed for non-contact Hall effect tube ignition system. The chip is driving an external NPN Darlington tube to control the ignition coil， obtaining a sufficient ignition energy， accompa

5、nied by only a small energy loss. The design of auto electronic ignition control chip contains 10 modules： The reference voltage module， hall input circuit module， overvoltage protection circuit module， dwell control cir

6、cuit module， current limit circuit module， control </p><p>　　This article focuses on the detailed analysis for the input module：， including the reference voltage module and Hall-effect transistor module afte

7、r the completion of the system design and circuit design， simulationing， and then complete the back-end design [1] as well as verification. </p><p>　　The device used in this article circuit are all bipolar d

8、evices， using 5 micron standard bipolar process. Because the overall circuit of the chip is very large， so the circuit is divided into several modules to design， Design approximate location of each module in the device b

9、efore the first planned， Given package structure according to the process line to adjust the position of each module devices and pads after the whole layout. This design gives the package shown in Figure 1. </p>&

10、lt;p>　　2 Circuit analysis， Simulation results and Layout design </p><p>　　（1） The reference voltage module </p><p>　　Functional Analysis： When V3 begin supply to the entire circuit， with the

11、the V3 elevated， Q58 conduction first， so Q60 conduction， Q57， Q58 constitute a Darlington transistor. As Q60 conduction， making the mirror current source Q59-1 and Q59-2 conduction， to supply the Bandgap reference compo

12、sition of the Q56，Q53 and R33， and finally a 1.25V reference voltage is generated at the base electrode of the Q38. After the reference voltage generator， the electric potential of base electrode of the Q61</p>&l

13、t;p>　　The key components in the reference voltage module： </p><p>　?、臫he area ratio should strictly match of Q53 and Q56， the size of R33 affect the reference voltage value. </p><p>　　⑵R27，R2

14、8 should strictly match. </p><p>　　The layout design of the reference voltage module： According to the tank to divide the standard cells， the transistors of the same collector potential can be placed in an i

15、solated area. So the reference voltage module circuit is divided into 10 isolated areas. Then to design devices in each isolated areas. </p><p>　　1. Design of the transistors </p><p>　　The desig

16、n of the chip should not only consider the performance of the circuit， but also consider the chip area， To try to make the minimum size of each device， Adjust the size of the transistor first. Although the size of the tr

17、ansistor is adjusted to the minimum， will increase the series resistance of the device and increase the time constant， but can reduce the chip area， Balance， the benefits of shrinking device sizes far greater than the ha

18、rm it brings[7]. </p><p>　　For the layout design of transistors， we must design a minimum size transistor first， this transistor is given according to the level of technology of the process line， the emitter

19、 area of the minimum size transistor is 14×14in this design， then consider the minimum spacing on this basis， gradually sets of synthetic a minimum size transistor， which is the standard transistor. </p><

20、p>　　According to the simulation of the circuit， calculates all the transistor emitter circuit size. Unit tube as the standard， calculates the emission area are N times the unit tube. Then according to the design rules

21、 ， layout each transistor. In addition to the area of strict matching of the transistor， the emitter area and shape must be strictly consistent， and close to the place. </p><p>　　Design of horizontal PNP tub

22、e sometimes uses split collector， single horizontal </p><p>　　PNP transistor is divided into several smaller， common emitter， This can effectively reduce the transistor area， As long as the collector of same

23、 shape， and are symmetrically placed， the difference is within 1%[8]. </p><p>　　2. Design of resistance </p><p>　　According to the resistance of different type has different sheet resistance， Th

24、e large resistance is designed of injection resistance， the small resistance is designed of diffusion resistance， the larger resistance is designed of an interlayer resistance. 　　According to the end process line and la

25、yout correction factor determined resistance shape and corner number. </p><p>　　There are 15 resistance in the module， through calculation and analysis， one is the base diffusion resistance， the rest is the

26、injected resistance. </p><p>　　3. Design of Capacitor </p><p>　　There is only one capacitor in this module， we can calculate its area： </p><p>　　To calculate the area of capacitor ，

27、we design this capacitor asa comb capacitor， </p><p>　　The overlapping area of P and N is 5000 ， to meet the requirement for the 2pF capacitance value. </p><p>　　After designing of each device i

28、n the module， low risk and rules can be combined to reduce area. Voltage reference module layout design as shown in figure 4. </p><p>　　3 Layout Verification </p><p>　　Universal integrated circu

29、it is basal designed by artificial at present， and because of the electrical properties and process conditions constraints automatic layout design can not get satisfactory results at a time， it often needs engineering mo

30、dification and supplement wiring. Because of the intervention of artificial land inevitably there will be some mistake. On the other hand， Because of many physical factors， compared with the logic design， circuit design

31、results， there will be some change</p><p>　　In this design， the layout were checked by DRC and LVS verification. DRC ensures the integrity of the layout design rule， LVS guarantees the consistency of the lay

32、out and circuit. </p><p>　　4 Conclusion </p><p>　　The design of electronic ignition control chip success， to fill the gaps in the domestic similar chip design， the chip occupies smaller area， lo

33、wer power consumption， so as to improve the utilization of the chip， save design cost. </p><p>　　Reference literature </p><p>　　[1] Chen Yun. Research LSI automatic layout design method [D]： [Ma

34、ster thesis]. Chengdu： University of Electronic Science and Technology， 2003 </p><p>　　[2] Chen Jinsong. Analog Integrated Circuits （theory， design， application） [M]. Beijing： China University of Science and

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38、iple of CMOS Circuit Power-Delay Optimization with Transistor Sizing[J]. Circuits and Systems，1996.ISCAS “96，Connecting the World”，1996 IEEE International Symposium on Volume 1，12-15 May 1996： 637～640 </p><p&g

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