單片機設(shè)計外文文獻(xiàn)翻譯（含中英文）

1、<p>　　附錄A 外文翻譯——AT89S52/AT89S51技術(shù)手冊</p><p><b>　　AT89S52譯文</b></p><p><b>　　主要性能</b></p><p>　　與MCS-51單片機產(chǎn)品兼容</p><p>　　8K字節(jié)在系統(tǒng)可編程Flash存儲器</

2、p><p><b>　　1000次擦寫周期</b></p><p>　　全靜態(tài)操作：0Hz～33Hz</p><p><b>　　三級加密程序存儲器</b></p><p>　　32個可編程I/O口線</p><p>　　三個16位定時器/計數(shù)器</p><p

3、><b>　　八個中斷源</b></p><p>　　全雙工UART串行通道</p><p>　　低功耗空閑和掉電模式</p><p><b>　　掉電后中斷可喚醒</b></p><p><b>　　看門狗定時器</b></p><p><

4、b>　　雙數(shù)據(jù)指針</b></p><p><b>　　掉電標(biāo)識符</b></p><p><b>　　功能特性描述</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K在系統(tǒng)可編程Flash 存儲器。使用Atmel公司高密度非易失性存儲器技術(shù)制造，與工業(yè)80C51

5、產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8位CPU和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的解決方案。AT89S52具有以下標(biāo)準(zhǔn)功能：8k字節(jié)Flash，256字節(jié)RAM，32位I/O口線，看門狗定時器，2個數(shù)據(jù)指針，三個16位定時器/計數(shù)器，一個6向量2級中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時鐘電路。另外，AT89S52可降至

6、0Hz靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機一切工作停止，直到下一個中斷或硬件復(fù)位為止。</p><p><b>　　引腳結(jié)構(gòu)</b></p><p><b>　　方框圖</b></p><p&

7、gt;<b>　　VCC : 電源</b></p><p><b>　　GND : 地</b></p><p>　　P0口：P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動8個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。當(dāng)訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻

8、。</p><p>　　在flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。</p><p>　　P1口：P1 口是一個具有內(nèi)部上拉電阻的8位雙向I/O 口，p1 輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P1端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（II

9、L）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗時，P1口接收低8位地址字節(jié)。</p><p>　　P2 口：P2 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P2端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，

10、被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2口送出高八位地址。在這種應(yīng)用中，P2口使用很強的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內(nèi)容。</p><p>　　在flash編程和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。</p>&

11、lt;p>　　P3 口：P3口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p2輸出緩沖器能驅(qū)動4個TTL 邏輯電平。對P3端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。在flash編程和校驗時，P3口也接收一些控制信號。</p><p>　　RST:

12、復(fù)位輸入。晶振工作時，RST腳持續(xù)2個機器周期高電平將使單片機復(fù)位?？撮T狗計時完成后，RST腳輸出96個晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認(rèn)狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/PROG：地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低8位地址的輸出脈沖。在flash編程時，此引腳也用作編程輸入脈沖。</p>

13、<p>　　在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。</p><p>　　如果需要，通過將地址為8EH的SFR的第0位置“1”，ALE操作將無效。這一位置“1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE 將被微弱拉高。這個ALE 使能標(biāo)志位（地址為8EH的SFR的第0位）的

14、設(shè)置對微控制器處于外部執(zhí)行模式下無效。</p><p>　　PSEN:外部程序存儲器選通信號是外部程序存儲器選通信號。</p><p>　　當(dāng) AT89S52從外部程序存儲器執(zhí)行外部代碼時，在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，將不被激活。</p><p>　　EA/VPP:訪問外部程序存儲器控制信號。為使能從0000H 到FFFFH的外部程序存儲器讀

15、取指令，必須接GND。</p><p>　　為了執(zhí)行內(nèi)部程序指令，應(yīng)該接VCC。</p><p>　　在flash編程期間，也接收12伏VPP電壓。</p><p>　　XTAL1:振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　XTAL2:振蕩器反相放大器的輸出端。</p><p><b>

16、;　　存儲器結(jié)構(gòu)</b></p><p>　　MCS-51器件有單獨的程序存儲器和數(shù)據(jù)存儲器。外部程序存儲器和數(shù)據(jù)存儲器都可以64K尋址。</p><p>　　程序存儲器：如果EA引腳接地，程序讀取只從外部存儲器開始。</p><p>　　對于89S52，EA如果接VCC，程序讀寫先從內(nèi)部存儲器（地址為0000H～1FFFH）開始，接著從外部尋址，尋址地

17、址為：2000H~FFFFH。</p><p><b>　　中斷</b></p><p>　　AT89S52有6個中斷源：兩個外部中斷和，三個定時中斷（定時器0、1、2）和一個串行中斷。這些中斷每個中斷源都可以通過置位或清除特殊寄存器IE中的相關(guān)中斷允許控制位分別使得中斷源有效或無效。IE還包括一個中斷允許總控制位EA，它能一次禁止所有中斷。IE.6位是不可用的。對于

18、AT89S52，IE.5位也是不能用的。用戶軟件不應(yīng)給這些位寫1。它們?yōu)锳T89系列新產(chǎn)品預(yù)留。</p><p>　　定時器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進(jìn)入中斷服務(wù)后，這些標(biāo)志位都可以由硬件清0。實際上，中斷服務(wù)程序必須判定是否是TF2 或EXF2激活中斷，標(biāo)志位也必須由軟件清0。</p><p>　　定時器0和定時器1標(biāo)志位TF0 和TF1在計數(shù)溢出的那

19、個周期的S5P2被置位。它們的值一直到下一個周期被電路捕捉下來。然而，定時器2的標(biāo)志位TF2在計數(shù)溢出的那個周期的S2P2被置位，在同一個周期被電路捕捉下來。</p><p><b>　　AT89S51譯文</b></p><p>　　AT89S51 (8位微控制單片機，片內(nèi)含4K bytes可系統(tǒng)編程的存儲器)</p><p>　　AT89S

20、51是美國ATMEL公司生產(chǎn)的低功耗，高性能CMOS 8位單片機，片內(nèi)含4k bytes的可系統(tǒng)編程的Flash只讀程序存儲器，器件采用ATMEL公司的高密度、非易失性存儲技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)8051指令系統(tǒng)及引腳。它集Flash程序存儲器既可在線編程（ISP)也可用傳統(tǒng)方法進(jìn)行編程及通用8位微處理器于單片芯片中，ATMEL公司的功能強大，低價位AT89S51單片機可為您提供許多高性價比的應(yīng)用場介，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)

21、：·與MCS-51 產(chǎn)品指令系統(tǒng)完全兼:容·4k字節(jié)在線系統(tǒng)編程(ISP) Flash閃速存儲器·1000次擦寫周期·4. 0---5. 5V的工作電壓范圍·全靜態(tài)工作模式：0Hz---33MHz·三級程序加密鎖·128×8字節(jié)內(nèi)部RAM·32個可編程I/O口線·2個16位定時/計數(shù)器·6個中斷源·

22、;全雙工串行UART通道·低功耗空閑和掉電模式·中斷可從空閑模式喚醒系統(tǒng)·看門狗(WDT)及雙數(shù)據(jù)指針·掉電標(biāo)識和快速編程特性·靈活的在線系統(tǒng)編程(ISP一字節(jié)或頁寫模式)功能特性概述：    AT89S51提供以下</p><p><b>　　AT89S52原文</b></p>&l

23、t;p><b>　　Features</b></p><p>　　? Compatible with MCS-51® Products</p><p>　　? 8K Bytes of In-System Programmable (ISP) Flash Memory</p><p>　　? 1000 Write/Erase Cy

24、cles</p><p>　　? Fully Static Operation: 0 Hz to 33 MHz</p><p>　　? Three-level Program Memory Lock</p><p>　　? 256 x 8-bit Internal RAM</p><p>　　? 32 Programmable I/O Lin

25、es</p><p>　　? Three 16-bit Timer/Counters</p><p>　　? Eight Interrupt Sources</p><p>　　? Full Duplex UART Serial Channel</p><p>　　? Low-power Idle and Power-down Modes&l

26、t;/p><p>　　? Interrupt Recovery from Power-down Mode</p><p>　　? Watchdog Timer</p><p>　　? Dual Data Pointer</p><p>　　? Power-off Flag</p><p>　　Description<

27、;/p><p>　　The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory t

28、echnology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combi

29、ning a versatile 8-bit CPU with in system programmable Flash on a monolithicchip</p><p>　　Pin Configurations</p><p>　　Block Diagram</p><p>　　Pin Description</p><p><

30、b>　　VCC</b></p><p>　　Supply voltage.</p><p><b>　　GND</b></p><p><b>　　Ground.</b></p><p><b>　　Port 0</b></p><p>

31、;　　Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.</p><p>　　Po

32、rt 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pull ups.</p><p>　　Port 0 also receives the cod

33、e bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri-fication.</p><p><b>　　Port 1</b></p><p>　　

34、Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as

35、 inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.</p><p>　　In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2

36、 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.</p><p>　　Port 1 also receives the low-order address bytes during Flash progr

37、amming and verification.</p><p><b>　　Port 2</b></p><p>　　Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.Wh

38、en 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups

39、.</p><p>　　Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX @ DPTR). In this application, Port 2

40、uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.</p><p>　　Port 2 als

41、o receives the high-order address bits and some control signals during Flash programming and verification.</p><p><b>　　Port 3</b></p><p>　　Port 3 is an 8-bit bidirectional I/O port w

42、ith internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,</p><p>　　P

43、ort 3 pins that are externally being pulled low will source current (IIL) because of the pullups. </p><p>　　Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the followi

44、ng table.</p><p>　　Port 3 also receives some control signals for Flash programming and verification.</p><p><b>　　RST</b></p><p>　　Reset input. A high on this pin for two

45、 machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature.

46、 In the default state of bit DISRTO,the RESET HIGH out feature </p><p>　　is enabled.</p><p>　　Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during access

47、es to external memory. This pin is also the program pulse input during Flash programming.</p><p>　　In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for

48、external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.</p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR locat

49、ion 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode.&

50、lt;/p><p>　　Program Store Enable is the read strobe to external program memory.</p><p>　　When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, exc

51、ept that two activations are skipped during each access to external data memory.</p><p>　　External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program mem

52、ory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed will be ternally latched on reset. should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt

53、programming enable voltage(VPP) during Flash programming.</p><p><b>　　XTAL1</b></p><p>　　Input to the inverting oscillator amplifier and input to the nternal clock operating circuit.

54、</p><p><b>　　XTAL2</b></p><p>　　Output from the inverting oscillator amplifier.</p><p>　　Special Function Registers</p><p>　　A map of the on-chip memory are

55、a called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in

56、 general return random data, and write accesses will have an indeterminate effect.</p><p>　　User software should not write 1s to these unlisted locations,since they may be used in future products to invokene

57、w features. In that case, the reset or nactive values of the new bits will always be 0.</p><p>　　Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (show

58、n in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.</p><p>　　Interrupt Registers: The individual int

59、errupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.</p><p>　　Timer 2 Operating Modes</p><p>　　In the Counter function,

60、the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high

61、 in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (

62、24 oscillator periods) are required</p><p>　　Interrupts</p><p>　　The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, a

63、nd 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE

64、also contains a global disable bit, EA, which</p><p>　　disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemente

65、d.</p><p>　　User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON.

66、Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to

67、 be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 </p><p><b>　　AT89S51原文</b></p><p>　　The AT89S51 is a low-power, high-performance CMOS 8-bit micro

68、controller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set

69、and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithi

70、c c</p><p>　　The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two一level int

71、errupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable po