x5045帶4kb spi eeprom 的cpu監(jiān)控器中英文翻譯

1、<p><b>　　附 錄 英文文獻(xiàn)</b></p><p>　　4K X5043/X5045 512 x 8 Bit</p><p>　　CPU Supervisor with 4K SPI EEPROM</p><p>　　DESCRIPTION</p><

2、p>　　These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, red

3、uces board space requirements, and increases reliability.</p><p>　　Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power

4、 supply and oscillator to stabilize before the processor executes code.</p><p>　　The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restar

5、t a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the po

6、wer.</p><p>　　The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted un

7、til VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to f

8、ine-tune the threshold for applications requiring higher precision.</p><p>　　The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s block lock protection. The array is internally organiz

9、ed as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.</p><p>　　The device utilizes Xicor’s proprietary Direct Write?cell, prov

10、iding a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.</p><p><b>　　FEATURES</b></p><p>　　? Selectable time out watchdog timer</p><p>&l

11、t;b>　　? Low VCC</b></p><p>　　detection and reset assertion</p><p>　　—Five standard reset threshold voltages</p><p>　　—Re-program low VCC</p><p>　　reset thresho

12、ld voltage</p><p>　　using special programming sequence.</p><p>　　—Reset signal valid to VCC= 1V</p><p>　　? Long battery life with low power consumption</p><p>　　—<50

13、µA max standby current, watchdog on</p><p>　　—<10µA max standby current, watchdog off</p><p>　　—<2mA max active current during read</p><p>　　? 2.7V to 5.5V and 4.5V

14、to 5.5V power supply</p><p><b>　　versions</b></p><p>　　? 4Kbits of EEPROM–1M write cycle endurance</p><p>　　? Save critical data with Block Lock?</p><p><

15、;b>　　memory</b></p><p>　　—Protect 1/4, 1/2, all or none of EEPROM array</p><p>　　? Built-in inadvertent write protection</p><p>　　—Write enable latch</p><p>　　

16、—Write protect pin</p><p>　　? 3.3MHz clock rate</p><p>　　? Minimize programming time</p><p>　　—16-byte page write mode</p><p>　　—Self-timed write cycle</p><p

17、>　　—5ms write cycle time (typical)</p><p>　　? SPI modes (0,0 & 1,1)</p><p>　　? Available packages</p><p>　　—8-lead MSOP, 8-lead SOIC, 8-pin PDIP</p><p>　　—14-lea

18、d TSSOP</p><p>　　PIN DESCRIPTIONS</p><p>　　Serial Output (SO)</p><p>　　SO is a push/pull serial data output pin. During a readcycle, data is shifted out on this pin. Data is clocked

19、 out by the falling edge of the serial clock.</p><p>　　Serial Input (SI)</p><p>　　SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on

20、this pin. Data is latched by the rising edge of the serial clock.</p><p>　　Serial Clock (SCK)</p><p>　　The Serial Clock controls the serial bus timing for data input and output. Opcodes, address

21、es, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.</p><p>　　Chip Select (CS)</p><p>　

22、　When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, pl

23、acing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation.</p><p>　　Write Protect (WP)</p><p>　　Wh

24、en WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally.When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still

25、 low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write.</p><p>　　Reset (RESET, RESET)</p><p>　　X5043/45,

26、 RESET/RESET is an active low/HIGH,open drain output which goes active whenever VCC falls below the minimum VCCsense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET a

27、lso goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer.</p><p>　　PRINCIPLES OF OPERATI

28、ON</p><p>　　Power On Reset</p><p>　　Application of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system mic

29、roprocessor from starting to operate with insuf-ficient voltage or prior to stabilization of the oscillator.</p><p>　　When VCC exceeds the device VTRIP value for 200ms(nominal) the circuit releases RESET/RES

30、ET, allowing the processor to begin executing code.</p><p>　　Low Voltage Monitoring</p><p>　　During operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply voltage fa

31、lls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also r

32、emains active until VCC returns and exceeds VTRIP for 200ms.</p><p>　　Watchdog Timer</p><p>　　The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The mic

33、roprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvo

34、latile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog time</p><p>　　VCC Threshold Res

35、et Procedure</p><p>　　The X5043/X5045 is shipped with a standard VCCthreshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the stan

36、dard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal

37、.</p><p>　　Setting the VTRIP Voltage</p><p>　　This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP</p><p>　　is 4.4V and the new VTRIP

38、 is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.</p><p>　　To set

39、the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command,followed by a write of Data 00h to address 01h.CS going HIGH on t

40、he write operation initiates the VTRIP programmingsequence. Bring WP LOW to complete the operation.</p><p>　　Note:This operation also writes 00h to array address 01h.</p><p>　　Resetting the VTRI

41、P Voltage</p><p>　　This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is r

42、eset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value.</p><p>　　To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to t

43、he programming voltage VP.Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence.Bring WP LOW to complete the operation.<

44、;/p><p>　　Note:This operation also writes 00h to array address 03h.</p><p>　　SPI Serial Memory</p><p>　　The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s bloc

45、k lock protection. The array is internally organized as x8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.</p><p>　　The devic

46、e utilizes Xicor’s proprietary Direct Write? cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.</p><p>　　The device is designed to interface directly with the

47、synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.</p><p>　　The device contains an 8-bit instruction register that controls the operation of the device. The instruction c

48、ode is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remai

49、nder of the operations require an instruction byte,an 8-bit address, then data bytes. All instruction,address and data bits are clocked by the SCK input. All instructions</p><p>　　Clock and Data Timing</p

50、><p>　　Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and th

51、en start it again to resume operations where left off. CS must be LOW during the entire operation.</p><p>　　Write Enable Latch</p><p>　　The device contains a Write Enable Latch. This latch must

52、be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch . This latch is automatically reset upon a power-up condition and after the completion o

53、f a valid byte, page, or status registerwrite cycle. The latch is also reset if WP is brought LOW.</p><p>　　When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data.<

54、/p><p>　　Status Register</p><p>　　The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory bl

55、ock lock protection. The Status Register is formatted as shown in “Status Register”.</p><p>　　Status Register: (Default = 30H)</p><p>　　The Write-In-Progress (WIP) bit is a volatile, read only b

56、it and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”

57、, no write is in progress.</p><p>　　The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a vol

58、atile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit.</p><p>　　The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile b

59、its are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It wi

60、ll remain protected until the BL bits are altered to disable block lock protection of that portion of memory.</p><p>　　The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvola

61、tile bits are programmed with the WRSR instruction.</p><p>　　Read Status Register</p><p>　　To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Th

62、en the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence . The Status Register may be read at any time, even during a Write Cycle.</p><p

63、>　　Write Status Register</p><p>　　Prior to any attempt to write data into the status register, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock th

64、e WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operatio

65、n ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored.</p><p>　　Read Memory Array</p><p>　　When reading from the EEPROM memory array, CS is fir

66、st pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opco

67、de and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next</p><p>　　address can be read sequentially by continuing to

68、provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $000 allowi

69、ng the read cycle to be continued indefi-nitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence .</p><p>　　Write Memory Array</p><p>　　Prior to any a

70、ttempt to write data into the memoryarray, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction . First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS L

71、OW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instruction contains address bit A8, which selects the upper or lower half of the array. If CS do

72、es not go HIGH between WREN and WRITE, the WRI</p><p>　　The WRITE operation requires at least 16 clocks. CS must go low and remain low for the duration of the operation. The host may continue to write up to

73、16 bytes of data. The only restriction is that the 16 bytes must reside within the same page. A page address begins with address [x xxxx 0000] and ends with [xxxxx 1111]. If the byte address reaches the last byte on the

74、page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been pr</p><p>　　For the write operation (byte or page write) to be completed,CS must

75、 be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed .</p><p>　　While the write is in pr

76、ogress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.</p><p>　　OPERATIONAL NOTES<

77、/p><p>　　The device powers-up in the following state:</p><p>　　– The device is in the low power standby state.</p><p>　　– A HIGH to LOW transition on CS is required to enter</p>

78、<p>　　an active state and receive an instruction.</p><p>　　– SO pin is high impedance.</p><p>　　– The Write Enable Latch is reset.</p><p>　　– The Flag Bit is reset.</p>

79、<p>　　– Reset Signal is active for tPURST.</p><p>　　Data Protection</p><p>　　The following circuitry has been included to prevent</p><p>　　inadvertent writes:</p><p

80、>　　– A WREN instruction must be issued to set the Write</p><p>　　Enable Latch.</p><p>　　– CS must come HIGH at the proper clock count in</p><p>　　order to start a nonvolatile wri

81、te cycle.</p><p>　　– Block Protect bits provide additional level of write</p><p>　　protection for the memory array.</p><p>　　– The WP pin LOW blocks nonvolatile write operations.<

82、;/p><p><b>　　中文翻譯</b></p><p>　　X5043 　　X5045</p><p>　　帶4Kb SPI EEPROM 的CPU監(jiān)控器</p><p><b>　　一、概述</b></p><p><b>　　1.1一般說(shuō)明：</b>

83、;</p><p>　　X5043/45把四種常用的功能：上電復(fù)位,看門狗定時(shí)器、電源電壓監(jiān)控和塊鎖（）保護(hù)的串行EEPROM存儲(chǔ)器組成在一個(gè)封裝內(nèi)。這種組合降低了系統(tǒng)的成本、減小了電路板空間和增加了可靠性。</p><p>　　向器件加電時(shí)激活了上電復(fù)位電路，它保持有效一段時(shí)間。這可是電源和振蕩器穩(wěn)定，然后微處理器再執(zhí)行代碼。</p><p>　　看門狗定時(shí)器對(duì)微

84、處理器提供一個(gè)獨(dú)立的保護(hù)機(jī)制。當(dāng)系統(tǒng)故障時(shí)，在可選的超時(shí)時(shí)間(time-out-interval)之后，器件將激活信號(hào)，用戶可以從三個(gè)預(yù)置的值中選擇一個(gè)超時(shí)時(shí)間。一旦選定，即使在斷電后重啟電源時(shí)也不會(huì)改變。</p><p>　　器件的低Vcc檢測(cè)電路，可以保護(hù)系統(tǒng)免受低電壓影響，當(dāng)Vcc轉(zhuǎn)換點(diǎn)以下時(shí)，系統(tǒng)復(fù)位。復(fù)位一直持續(xù)到Vcc回到正常工作電平并且穩(wěn)定為止。有5個(gè)工業(yè)標(biāo)準(zhǔn)轉(zhuǎn)換電壓門限可以選用，并且Xicor獨(dú)

85、特的電路允許對(duì)門限編程以滿足用戶的需要或者對(duì)高精度應(yīng)用的精細(xì)調(diào)整的需要。</p><p>　　X5042/45的存儲(chǔ)器部分時(shí)具有Xicor塊鎖保護(hù)的COMS 4Kb串行EEPROM。該陣列內(nèi)部的組織是×8。器件具有SPI接口特性，其軟件協(xié)議允許工作在一個(gè)簡(jiǎn)單的四線總線上。</p><p>　　器件利用了Xicor公司專有的Direct晶片，提供最小為1000000次擦寫和最少10

86、0年的數(shù)據(jù)保存期。</p><p><b>　　1.2特點(diǎn)：</b></p><p>　　可選用的看門狗定時(shí)器</p><p>　　低Vcc檢測(cè)并產(chǎn)生復(fù)位</p><p>　　——五種標(biāo)準(zhǔn)的復(fù)位門限電壓</p><p>　　――用專用的編號(hào)順序調(diào)整低Vcc復(fù)位門限電壓</p><

87、;p>　　――復(fù)位信號(hào)有效至Vcc＝1V</p><p><b>　　低功耗使電池壽命長(zhǎng)</b></p><p>　　――看門狗工作時(shí)，等待電流小于50uA（最大）</p><p>　　――看門狗停止時(shí)，等待電流小于10uA(最大)</p><p>　　――當(dāng)讀數(shù)時(shí)工作電流小于2mA（最大）</p>

88、<p>　　4KEEPROM可進(jìn)行一百萬(wàn)次擦寫</p><p>　　用塊鎖保護(hù)保存重要的數(shù)據(jù)</p><p>　　――可保護(hù)EEPROM陣列的1、1/4、1/2或全部</p><p>　　內(nèi)建偶然性的（inadvertent）寫保護(hù)</p><p><b>　　――寫使能鎖存</b></p>&l

89、t;p><b>　　――寫保護(hù)引腳</b></p><p>　　3.3MHz 時(shí)鐘率</p><p><b>　　減少編程時(shí)間</b></p><p>　　――16字節(jié)的寫方式</p><p><b>　　――自定時(shí)間寫周期</b></p><p>

90、;　　――5ms寫周期（電性）</p><p>　　SPI方式（0，0和1，1）</p><p><b>　　可供封裝</b></p><p>　　――8引腳SOIC,　8引腳MSOP，8引腳PDIP</p><p>　　――14引腳TSSO</p><p>　　1.3引腳排列及引腳說(shuō)明：<

91、/p><p><b>　　SO</b></p><p>　　SO是一個(gè)串行數(shù)據(jù)推/挽輸出端。當(dāng)讀周期時(shí)，數(shù)據(jù)從該腳移出。數(shù)據(jù)由串行時(shí)鐘的下降沿同步輸出。</p><p><b>　　SI</b></p><p>　　SI是串行數(shù)據(jù)輸入端。所有要寫入存儲(chǔ)器的操作碼、字節(jié)地址和數(shù)據(jù)都從該引腳輸入。輸入信號(hào)由

92、串行時(shí)鐘的上升沿鎖存。</p><p><b>　　SCK</b></p><p>　　SCK是串行時(shí)鐘端。串行時(shí)鐘控制串行總線數(shù)據(jù)輸入和輸出的時(shí)序。出現(xiàn)在SI引腳的操作碼、地址或數(shù)據(jù)在輸入的上升沿被鎖存，而SO引腳上的數(shù)據(jù)在輸入時(shí)鐘的下降沿之后改變。</p><p><b>　　CS</b></p><

93、;p>　　是片選端，當(dāng)為高時(shí)，X5043/45未被選中，SO輸出端處于高阻抗?fàn)顟B(tài)；除非正在進(jìn)行內(nèi)部寫操作，器件將處于等待方式。為低即使能X5043/45，將它置于激活方式。必須注意：當(dāng)上電之后，任何操作開(kāi)始之前，需要先在上有一次由高至低的跳變。</p><p><b>　　WP</b></p><p>　　寫保護(hù)端。當(dāng)為低時(shí)，向X5043/45的非易失性寫被禁止

94、，但器件其它功能正常。當(dāng)保持高時(shí)，所有功能包括非易失性寫操作都正常。在保持為低時(shí)變低將中斷向X5043/45的一次寫入。如果內(nèi)部寫周期已經(jīng)開(kāi)始，變低對(duì)寫操作沒(méi)有影響。</p><p>　　復(fù)位輸出。是低/高有效的漏極開(kāi)路輸出器，只要Vcc下降至低于最小Vcc檢測(cè)電平時(shí)輸出端變?yōu)橛行АＫ鼘⒈３钟行е抵罺cc上升到最小Vcc檢測(cè)電平200ms為止，如果看門狗定時(shí)器的使能有而且SDA保持HIGH或LOW的時(shí)間長(zhǎng)于選定的

95、看門狗定時(shí)器時(shí)間，則將變?yōu)橛行г谟幸幌陆颠厡?fù)位看門狗定時(shí)器</p><p><b>　　二、工作原理</b></p><p><b>　　2.1上電復(fù)位</b></p><p>　　向X5043/45加電是會(huì)激活一個(gè)“上電復(fù)位電路”，它將使引腳有效。這個(gè)信號(hào)有幾種用途：</p><p>　　――它

96、避免系統(tǒng)的微處理器在電壓不足的情況下工作。</p><p>　　――它避免微處理器在振蕩器穩(wěn)定前工作。</p><p>　　當(dāng)Vcc超時(shí)器件的門限值，經(jīng)200ms（典型）電路釋放，允許系統(tǒng)開(kāi)始工作。</p><p><b>　　2.2低電壓監(jiān)視</b></p><p>　　在工作時(shí)，X5043/45監(jiān)視Vcc電平，如果電

97、源電壓跌落到預(yù)置的最小以下時(shí)，即確認(rèn)。信號(hào)避免了微處理器工作在電源失效或斷開(kāi)的情況下。信號(hào)保持有效值直到電壓跌落到低于1V。它也保持有效值直到Vcc返回并超過(guò)經(jīng)200ms時(shí)。</p><p>　　2.3 看門狗定時(shí)器</p><p>　　看門狗定時(shí)器電路通過(guò)監(jiān)視WDI輸入來(lái)監(jiān)視微處理器是否激活。微處理器必須周期性的觸發(fā)/WDI引腳以避免信號(hào)。/WDI引腳必須在看門狗超時(shí)時(shí)間終止之前受到由高

98、至低信號(hào)的觸發(fā)。在狀態(tài)寄存器中的兩個(gè)非易失控制位可以決定看門狗的超時(shí)周期。微處理器可以改變這些看門狗控制位。沒(méi)有位控制器的作用，看門狗定時(shí)器的控制位保持不變，即使是當(dāng)全部電源故障時(shí)。</p><p>　　2.4 重新設(shè)置Vcc門限的步驟</p><p>　　X5043/45是出廠時(shí)是處于標(biāo)準(zhǔn)的Vcc門限電壓。這個(gè)標(biāo)準(zhǔn)值在正常和存儲(chǔ)時(shí)是不會(huì)改變的，但是在應(yīng)用中，當(dāng)標(biāo)準(zhǔn)的并不恰當(dāng)時(shí)，或者需要更

99、精確的值時(shí)，X5043/45的門限是可以調(diào)整的，這要用到一個(gè)高電壓控制信號(hào)，其步驟說(shuō)明如下。</p><p><b>　　2.5 電壓的設(shè)置</b></p><p>　　該步驟用來(lái)設(shè)置為更高的電壓值。例如，如果當(dāng)前的是4.4V而新的為4.6V，本步驟將直接使之改變。如果新的設(shè)置是低于當(dāng)前的設(shè)置，則在設(shè)置新值之前先要復(fù)位跳變點(diǎn)。</p><p>

100、　　為了設(shè)置新的電壓，加需要的門限電壓至Vcc引腳以及編程電壓Vp至引腳。然后送WEN命令，接著向地址01h寫入數(shù)據(jù)00h.操作時(shí)變高將啟動(dòng)，的編程方式過(guò)程。</p><p>　　注意：該操作也向地址01h寫入00h.。</p><p>　　2.5.1 電壓的重新設(shè)置</p><p>　　該步驟用來(lái)設(shè)置至一個(gè)“原始”電壓的電平。例如，如果當(dāng)前的是4.4V而新的必須是

101、4.0V，則必須被復(fù)位。當(dāng)被復(fù)位時(shí)，新的將稍小于1.7V，為了設(shè)置電壓至一個(gè)較低的電平，必須使用本步驟。</p><p>　　為了復(fù)位電壓，加至少3V至Vcc引腳并將WP引腳接至編程電壓Vp。然后送一個(gè)WREN命令，接著向地址03h寫入數(shù)據(jù)00h，寫操作時(shí)變高將啟動(dòng)的編程過(guò)程。將WP置為低電平將完成該操作。</p><p>　　注意：該操作也向地址03h,寫入00h</p>

102、<p>　　2.6 SPI串行存儲(chǔ)器</p><p>　　器件的存儲(chǔ)器部份是帶有Xicor公司的塊鎖保護(hù)的COMS串行EEPROM陣列。陣列的內(nèi)部組織是×8位。器件具有串行外圍接口（SPI）和軟件協(xié)議的特點(diǎn)，允許在簡(jiǎn)單的四線總線上工作。器件利用Xicor專有的直接寫入晶片，提供最小為1000000次擦寫和最少為100年的數(shù)據(jù)保存期。器件設(shè)計(jì)成可直接與很多通用微控制器系列的同步SPI接口。<

103、;/p><p>　　器件包括一個(gè)控制器工作的8位指令寄存器。指令代碼通過(guò)SI輸入端寫入寄存器中，有兩種只需要指令字節(jié)的寫操作。有兩種用指令字節(jié)來(lái)啟動(dòng)數(shù)據(jù)輸入的讀操作。剩下的操作需要一個(gè)指令字節(jié)，一個(gè)8位地址，然后數(shù)據(jù)字節(jié)。所有的指令，地址和數(shù)據(jù)位都由SCK信號(hào)輸入。所有的指令、地址和數(shù)據(jù)的傳送都是MSB在前。</p><p>　　2.7 時(shí)鐘和數(shù)據(jù)時(shí)序</p><p>

104、　　在變低以后，在SI線上的輸入數(shù)據(jù)在SCK的第一個(gè)上升沿時(shí)鎖存。在SO線上的數(shù)據(jù)由SCK的下降沿輸出。允許用戶停止時(shí)鐘，然后再啟動(dòng)它以便在它停止的地方恢復(fù)操作。在整個(gè)工作期間必須為低。</p><p><b>　　2.8 寫使能鎖存</b></p><p>　　器件有一個(gè)寫使能鎖存（Write Enable Latch）功能。在一次寫操作開(kāi)始以前這個(gè)鎖存必須被設(shè)置。

105、WREN指令將設(shè)置該鎖存而WRDI指令將復(fù)位該鎖存該鎖存在一次上電和一次有效的字節(jié)、頁(yè)或狀態(tài)寄存器的寫操作完成后自動(dòng)地復(fù)位。如果被來(lái)低該鎖存也復(fù)位。</p><p>　　當(dāng)發(fā)出一個(gè)WREN、WRD或RESR命令時(shí)，不需要送一個(gè)字節(jié)的地址或數(shù)據(jù)。</p><p><b>　　2.9 狀態(tài)寄存器</b></p><p>　　狀態(tài)器存器包含四個(gè)非易失