外文翻譯--at89s52的功能介紹

1、<p><b>　　附錄</b></p><p><b>　　外文資料</b></p><p><b>　　英文部分：</b></p><p>　　The function introduction of AT89S52</p><p>　　Features(R) &

2、lt;/p><p>　　* Compatible with MCS-51 Products</p><p>　　* 8K Bytes of In-System Programmable (ISP) Flash Memory</p><p>　　– Endurance: 1000 Write/Erase Cycles</p><p>　　* 4.0

3、V to 5.5V Operating Range</p><p>　　* Fully Static Operation: 0 Hz to 33 MHz</p><p>　　* Three-level Program Memory Lock</p><p>　　* 256 x 8-bit Internal RAM</p><p>　　* 32

4、 Programmable I/O Lines</p><p>　　* Three 16-bit Timer/Counters</p><p>　　* Eight Interrupt Sources</p><p>　　* Full Duplex UART Serial Channel</p><p>　　* Low-power Idle a

5、nd Power-down Modes</p><p>　　* Interrupt Recovery from Power-down Mode</p><p>　　* Watchdog Timer</p><p>　　* Dual Data Pointer</p><p>　　* Power-off Flag</p><p

6、>　　Description：</p><p>　　The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density

7、 nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin-out .The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile mem

8、ory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic </p><p>　　The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/

9、O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is desi

10、gned with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,</p><p>　　Pin Descripti

11、on：</p><p>　　VCC：Supply voltage.</p><p>　　GND：Ground.</p><p>　　Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. Wh

12、en 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this

13、 mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pul</p><p>　　Port 1：Port 1 is an 8-bit bidirecti

14、onal I/O port with internal pull-ups . The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Po

15、rt 1 pins that are externally being pulled low will source because of the internal pull-ups. current (I IL) In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the ti

16、mer/counter 2 trigger inp</p><p>　　Port Pin Alternate Functions</p><p>　　P1.0 T2 (external count input to Timer/Counter 2), clock-out</p><p>　　P1.1 T2EX (Tim

17、er/Counter 2 capture/reload trigger and direction control)</p><p>　　P1.5 MOSI (used for In-System Programming)</p><p>　　P1.6 MISO (used for In-System Programming)</p>&l

18、t;p>　　P1.7 SCK (used for In-System Programming)</p><p>　　Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups . The Port 2 output buffers can sink/source four TTL inputs .When

19、1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs ,Port 2 pins that are externally being pulled low will source because of the internal pull-ups .current (I

20、 IL) Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use</p><p>　　Port 3：Port 3 is an 8-bit bidirectional I/O port with i

21、nternal pull-ups .The Port 3 output buffers can sink/source four TTL inputs .When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs , Port 3 pins that are e

22、xternally being pulled low will source because of the pull-ups .current (I IL) Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table .Port 3 also receives some contr

23、ol si</p><p>　　Port Pin Alternate Functions</p><p>　　P3.0 RXD (serial input port)</p><p>　　P3.1 TXD (serial output port)</p><

24、p>　　P3.2 INT0 (external interrupt 0)</p><p>　　P3.3 INT1 (external interrupt 1)</p><p>　　P3.4 T0 (timer 0 external input)</p><p>　　P3.

25、5 T1 (timer 1 external input)</p><p>　　P3.6 WR (external data memory write strobe)</p><p>　　P3.7 RD (external data memory read strobe)</p><

26、;p>　　RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 96 oscillator periods after the Watchdog times out .The DISRTO bit in SFR AUX

27、R (address 8EH) can be used to disable this feature. In the default state of bit DISRTO , the RESET HIGH out feature is enabled.</p><p>　　ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching t

28、he low byte of the address during accesses to external-memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of</p><p>　　1/6

29、 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by se

30、tting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in ex

31、ternal execution mode.</p><p>　　PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external pro- gram memory, PSEN is activated twice each

32、 machine activations are skipped during cycle, except that two PSEN each access to external data memory.</p><p>　　EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fe

33、tch code from external pro-gram memory locations starting at 0000H up to FFFFH. EA will be</p><p>　　Note, however, that if lock bit 1 is programmed, internally latched on reset. EA should be strapped to V CC

34、 for internal program executions .This pin also receives the 12-volt programming enable volt-age (V PP) during Flash programming.</p><p>　　XTAL1：Input to the inverting oscillator amplifier and input to the i

35、nternal clock operating circuit.</p><p>　　XTAL2：Output from the inverting oscillator amplifier.</p><p>　　Special Function Registers：A map of the on-chip memory area called the Special Function R

36、egister (SFR) space is shown in Table 1.</p><p>　　Table 1 . AT89S52 SFR Map and Reset Values</p><p>　　Note that not all of the addresses are occupied, and unoccupied addresses may not be implem

37、ented on the chip .Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may

38、be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.</p><p>　　Timer 2 Registers: Control and status bits are contained in registers

39、T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.</p><p>　　

40、Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.</p><p>　　Table 2 . </p><p>

41、　　Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0

42、 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.</p><p>　　Table 3 a. AUXR: Auxil

43、iary Register：</p><p>　　Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not af

44、fected by reset.</p><p>　　Table 3 b. AUXR1: Auxiliary Register 1：</p><p>　　Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of e

45、xternal Program and Data Memory can be addressed.</p><p>　　Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC , p

46、rogram fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.</p><p>　　Data Memory：The AT89S52 implements 256 bytes of o

47、n-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.

48、Data Memory The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR s

49、pace but ar</p><p>　　For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).</p><p>　　MOV 0A0H, #data</p><p>　　Instructions that us

50、e indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

51、</p><p>　　MOV @R0, #data</p><p>　　Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack space.</p><p>　　Watchdog

52、 Timer： (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRS

53、T) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every mach

54、ine cycle while the oscillator is running. The WDT t</p><p>　　Using the WDT：To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled,

55、 the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increm

56、ent every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To </p><p>　　WDT During Power-down and Idle：In Power-down mode the oscillat

57、or stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external inter

58、rupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an inter&l

59、t;/p><p>　　Timer 0 and 1：Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. </p><p>　　Timer 2：Timer 2 is a 16-bit Timer/Counter that can oper

60、ate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate g

61、enerator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 osc

62、illat</p><p>　　Capture Mode：In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can the

63、n be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, r

64、espectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The</p><p>　　Auto-reload (Up or Down Counter)：Timer 2 can be programmed to count up or down when configured in its 16-bit

65、auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Tim

66、er 2 can count up or down, depending on the value of the T2EX pin.</p><p>　　There are many function of AT89S52.This article was only a part of particular presentation of AT89S52.</p><p><b>

67、;　　中文部分：</b></p><p>　　AT89S52的功能介紹</p><p><b>　　主要性能 ：</b></p><p>　　? 與MCS-51單片機產(chǎn)品兼容 </p><p>　　? 8K字節(jié)在系統(tǒng)可編程Flash存儲器 </p><p>　　? 1000次擦寫周期

68、</p><p>　　? 全靜態(tài)操作：0Hz～33Hz </p><p>　　? 三級加密程序存儲器 </p><p>　　? 32個可編程I/O口線 </p><p>　　? 三個16位定時器/計數(shù)器 </p><p><b>　　? 八個中斷源 </b></p><p>

69、;　　? 全雙工UART串行通道 </p><p>　　? 低功耗空閑和掉電模式 </p><p>　　? 掉電后中斷可喚醒 </p><p><b>　　? 看門狗定時器 </b></p><p><b>　　? 雙數(shù)據(jù)指針 </b></p><p><b>　　

70、? 掉電標(biāo)識符</b></p><p><b>　　功能特性描述： </b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K 在系統(tǒng)可編程 Flash 存儲器。使用 Atmel 公司高密度非易失性存儲器技術(shù)制造，與工業(yè) 80C51 產(chǎn)品指令和引腳完全容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯

71、片上，擁有靈巧的 8 位 CPU 和在系統(tǒng)可編程Flash，使得 AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的解決方案。</p><p>　　AT89S52具有以下標(biāo)準(zhǔn)功能： 8k字節(jié)Flash，256字節(jié)RAM，32 位 I/O口線，看門狗定時器，2 個數(shù)據(jù)指針，三個 16 位定時器/計數(shù)器，一個6向量 2級中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時鐘電路。另外，AT89S52 可降至 0Hz 靜態(tài)邏輯

72、操作，持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機一切工作停止，直到下一個中斷或硬件復(fù)位為止。</p><p><b>　　管腳介紹：</b></p><p>　　VCC : 電源 </p><p><b>　　GND:

73、地 </b></p><p>　　P0 口：P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動8個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。 當(dāng)訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。 在 flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。 </p>

74、<p>　　P1 口：P1 口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口，p1 輸出緩沖器能驅(qū)動 4 個TTL 邏輯電平。對 P1 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（I IL）。 此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。 在

75、flash編程和校驗時，P1口接收低8位地址字節(jié)。 </p><p>　　引腳號 第二功能 </p><p>　　P1.0 T2（定時器/計數(shù)器T2的外部計數(shù)輸入），時鐘輸出 </p><p>　　P1.1 T2EX（定時器/計數(shù)器T2的捕捉/重載觸發(fā)信號和方向控制）</p><p>　　P1.5

76、 MOSI（在系統(tǒng)編程用） </p><p>　　P1.6 MISO（在系統(tǒng)編程用） </p><p>　　P1.7 SCK（在系統(tǒng)編程用） </p><p>　　P2 口：P2 口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口，P2 輸出緩沖器能驅(qū)動 4 個TTL 邏輯電平。對 P2 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此

77、時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（I IL）。 在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2 口送出高八位地址。在這種應(yīng)用中，P2 口使用很強的內(nèi)部上拉發(fā)送 1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內(nèi)容。 在flash編程和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。</p>

78、<p>　　P3 口：P3 口是一個具有內(nèi)部上拉電阻的 8 位雙向 I/O 口，p2 輸出緩沖器能驅(qū)動 4 個TTL 邏輯電平。對 P3 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（I IL）。 P3口亦作為AT89S52特殊功能（第二功能）使用，如下表所示。 在flash編程和校驗時，P3口也接收一些控制信號。</p><

79、;p>　　引腳號 第二功能 </p><p>　　P3.0 RXD（串行輸入） </p><p>　　P3.1 TXD（串行輸出） </p><p>　　P3.2 INT0(外部中斷 0) </p><p>　　P3.3 INT0(外部中斷 0) </

80、p><p>　　P3.4 T0（定時器0外部輸入） </p><p>　　P3.5 T1（定時器1外部輸入） </p><p>　　P3.6 WR(外部數(shù)據(jù)存儲器寫選通) </p><p>　　P3.7 RD(外部數(shù)據(jù)存儲器寫選通) </p><p>　　R

81、ST: 復(fù)位輸入。晶振工作時，RST腳持續(xù)2 個機器周期高電平將使單片機復(fù)位。看門狗計時完成后，RST 腳輸出 96 個晶振周期的高電平。特殊寄存器 AUXR(地址 8EH)上的DISRTO位可以使此功能無效。DISRTO默認(rèn)狀態(tài)下，復(fù)位高電平有效。</p><p>　　ALE/PROG：地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低 8 位地址的輸出脈沖。在flash編程時，此引腳（PROG）也用作編

82、程輸入脈沖。 在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。 如果需要，通過將地址為8EH的SFR的第0位置 “1”，ALE操作將無效。這一位置 “1”，ALE僅在執(zhí)行 MOVX 或MOVC指令時有效。否則，ALE將被微弱拉高。這個 ALE使能標(biāo)志位（地址為8EH的SFR的第0位）的設(shè)置對微控制器處于外部執(zhí)行模式下無效。</

83、p><p>　　PSEN:外部程序存儲器選通信號（PSEN）是外部程序存儲器選通信號。當(dāng) AT89S52從外部程序存儲器執(zhí)行外部代碼時，PSEN在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，PSEN將不被激活。</p><p>　　EA/VPP:訪問外部程序存儲器控制信號。為使能從0000H 到FFFFH的外部程序存儲器讀取指令，EA必須接GND。 為了執(zhí)行內(nèi)部程序指令，EA應(yīng)該接V C

84、C 。 在flash編程期間，EA也接收12伏V PP電壓。 </p><p>　　XTAL1:振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。 </p><p>　　XTAL2:振蕩器反相放大器的輸出端。</p><p>　　特殊功能寄存器 ； 特殊功能寄存器(SFR)的地址空間映象如表1所示。</p><p><b>　　表一：&

85、lt;/b></p><p>　　并不是所有的地址都被定義了。片上沒有定義的地址是不能用的。讀這些地址，一般將得到一個隨機數(shù)據(jù)；寫入的數(shù)據(jù)將會無效。 用戶不應(yīng)該給這些未定義的地址寫入數(shù)據(jù)“1”。由于這些寄存器在將來可能被賦予新的功能，復(fù)位后，這些位都為“0”。 </p><p>　　定時器 2 寄存器：寄存器T2CON 和 T2MOD 包含定時器 2 的控制位和狀態(tài)位（如表 2和表3

86、所示），寄存器對RCAP2H和RCAP2L是定時器2的捕捉/自動重載寄存器。 </p><p>　　中斷寄存器：各中斷允許位在IE寄存器中，六個中斷源的兩個優(yōu)先級也可在IE中設(shè)置。</p><p><b>　　表二：</b></p><p>　　雙數(shù)據(jù)指針寄存器：為了更有利于訪問內(nèi)部和外部數(shù)據(jù)存儲器，系統(tǒng)提供了兩路16位數(shù)據(jù)指針寄存器。位于SF

87、R中82H~83H的 DP0和位于84H～85。特殊寄存器 AUXR1中 DPS＝0 選擇 DP0；DPS=1 選擇 DP1。用戶應(yīng)該在訪問數(shù)據(jù)指針寄存器前先初始化DPS至合理的值。</p><p>　　表 3a AUXR：輔助寄存器 </p><p>　　掉電標(biāo)志位：掉電標(biāo)志位（POF）位于特殊寄存器PCON的第四位（PCON.4）。上電期間POF置“1”。POF可以軟件控制使用與否

88、，但不受復(fù)位影響。</p><p>　　表 3b AUXR1：輔助寄存器1</p><p>　　存儲器結(jié)構(gòu) ：MCS-51器件有單獨的程序存儲器和數(shù)據(jù)存儲器。外部程序存儲器和數(shù)據(jù)存儲器都可以64K尋址。 </p><p>　　程序存儲器：如果EA引腳接地，程序讀取只從外部存儲器開始。 對于89S52，如果 EA 接 V CC，程序讀寫先從內(nèi)部存儲器（地址為 00

89、00H～1FFFH）開始，接著從外部尋址，尋址地址為：2000H~FFFFH。 </p><p>　　數(shù)據(jù)存儲器：AT89S52 有 256 字節(jié)片內(nèi)數(shù)據(jù)存儲器。高 128 字節(jié)與特殊功能寄存器重疊。也就是說高128字節(jié)與特殊功能寄存器有相同的地址，而物理上是分開的。 當(dāng)一條指令訪問高于 7FH 的地址時，尋址方式?jīng)Q定 CPU 訪問高 128 字節(jié) RAM 還是特殊功能寄存器空間。直接尋址方式訪問特殊功能寄存器（

90、SFR）。</p><p>　　例如，下面的直接尋址指令訪問0A0H（P2口）存儲單元 </p><p>　　MOV 0A0H , #data </p><p>　　使用間接尋址方式訪問高 128 字節(jié) RAM。例如，下面的間接尋址方式中，R0 內(nèi)容為0A0H，訪問的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。 </p>&

91、lt;p>　　MOV @R0 , #data </p><p>　　堆棧操作也是簡介尋址方式。因此，高128字節(jié)數(shù)據(jù)RAM也可用于堆棧空間。</p><p>　　看門狗定時器 ：WDT是一種需要軟件控制的復(fù)位方式。WDT 由13位計數(shù)器和特殊功能寄存器中的看門狗定時器復(fù)位存儲器（WDTRST）構(gòu)成。WDT 在默認(rèn)情況下無法工作；為了激活WDT，戶用必須往 WDTRST 寄存

92、器（地址：0A6H）中依次寫入 01EH 和 0E1H。當(dāng)WDT激活后，晶振工作，WDT在每個機器周期都會增加。WDT計時周期依賴于外部時鐘頻率。除了復(fù)位（硬件復(fù)位或WDT溢出復(fù)位），沒有辦法停止WDT工作。當(dāng) WDT溢出，它將驅(qū)動RSR引腳一個高個電平輸出。</p><p>　　WDT 的使用 ：為了激活 WDT，用戶必須向 WDTRST寄存器（地址為0A6H的SFR）依次寫入0E1H和0E1H。當(dāng) WDT激活

93、后，用戶必須向 WDTRST寫入01EH和0E1H喂狗來避免 WDT溢出。當(dāng)計數(shù)達到 8191(1FFFH)時，13 位計數(shù)器將會溢出，這將會復(fù)位器件。晶振正常工作、WDT激活后，每一個機器周期 WDT 都會增加。為了復(fù)位 WDT，用戶必須向WDTRST 寫入 01EH 和 0E1H（WDTRST 是只讀寄存器）。WDT 計數(shù)器不能讀或?qū)?。?dāng) WDT 計數(shù)器溢出時，將給 RST 引腳產(chǎn)生一個復(fù)位脈沖輸出，這個復(fù)位脈沖持續(xù) 96個晶振周期

94、（TOSC），其中 TOSC=1/FOSC。為了很好地使用 WDT，應(yīng)該在一定時間內(nèi)周期性寫入那部分代碼，以避免WDT復(fù)位。在掉電模式下，晶振停止工作，這意味這WDT也停止了工作。在這種方式下，用戶不必喂狗。有兩種方式可以離開掉電模式：硬件復(fù)位或通過一個激活的外部中斷。通過硬件復(fù)位退出掉電模式后，用戶就應(yīng)該給 WDT 喂狗，就如同通常 AT89S52 復(fù)位一樣。通過中斷退出掉電模式的情形有很大的不同。中斷應(yīng)持續(xù)拉低很長一段</p&

95、gt;<p>　　定時器 0 和定時器 1 ：在 AT89S52 中，定時器 0 和定時器 1 的操作與 AT89C51 和 AT89C52 一樣。 </p><p>　　定時器 2 ：定時器2是一個16位定時/計數(shù)器，它既可以做定時器，又可以做事件計數(shù)器。其工作方式由特殊寄存器T2CON中的 C/T2位選擇。定時器 2有三種工作模式：捕捉方式、自動重載（向下或向上計數(shù)）和波特率發(fā)生器。工作模式由T

96、2CON中的相關(guān)位選擇。定時器2 有2 個8位寄存器：TH2和TL2。在定時工作方式中，每個機器周期，TL2 寄存器都會加 1。由于一個機器周期由 12 個晶振周期構(gòu)成，因此，計數(shù)頻率就是晶振頻率的1/12。在計數(shù)工作方式下，寄存器在相關(guān)外部輸入角 T2 發(fā)生 1 至 0 的下降沿時增加 1。在這種方式下，每個機器周期的S5P2期間采樣外部輸入。一個機器周期采樣到高電平，而下一個周期采樣到低電平，計數(shù)器將加 1。在檢測到跳變的這個周期的

97、 S3P1 期間，新的計數(shù)值出現(xiàn)在寄存器中。因為識別1－0的跳變需要2個機器周期（24個晶振周期），所以，最大的計數(shù)頻率不高于晶振頻率的 1/24。為了確保給定的電平在改變前采樣到一次，電平應(yīng)該至少在一個完整的機器周期內(nèi)保持不變。</p><p>　　捕捉方式 ：在捕捉模式下，通過T2CON中的EXEN2來選擇兩種方式。如果EXEN2=0，定時器2時一個16位定時/計數(shù)器，溢出時，對T2CON 的TF2標(biāo)志置位，

98、TF2引起中斷。如果EXEN2=1，定時器2做相同的操作。除上述功能外，外部輸入T2EX引腳（P1.1）1至0的下跳變也會使得TH2和TL2中的值分別捕捉到RCAP2H和RCAP2L中。除此之外，T2EX 的跳變會引起 T2CON 中的 EXF2 置位。像 TF2 一樣，T2EX 也會引起中斷。</p><p>　　自動重載 ：當(dāng)定時器 2 工作于 16 位自動重載模式，可對其編程實現(xiàn)向上計數(shù)或向下計數(shù)。這一功能